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Title: :  FPGA Based 64X64 MAC Design Using Vedic Multiplier and DKG Adder
PaperId: :  8958
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 4 Issue 4 2018
DUI:    16.0415/IJARIIE-8958
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
P. DIVYASRI KRISHNADEVARAYA ENGINEERING COLLEGE, GOOTY
E.C. RAMAKRISHNASRI KRISHNADEVARAYA ENGINEERING COLLEGE, GOOTY

Abstract

Electrical and Electronics Engineering
PPG, PPA, MAC, DSP
A multiplying block operate may be concededin 3 totally different ways: standard addition, partial product addition (PPA) and eventually partial product Generation (PPG).The two bud vase materials that must be considered are raising the speed of MAC which is accumulator block partial and product reduction. The 64 bitMAC design which will make use of Vedic multiplier and reversible logic gate can be accomplished in two stages.Firstly, multiplier stage, where a usual multiplier is replaced by Vedic multiplier using UrdhavaTriyagbhayam sutrafrom Vedic Mathematics. Multiplication is the primary operation of MAC unit. Speed, area, Power dissipation,consumption and latency are the major concerns in the multiplier stage. So, to evade them, we are going to selectquick multipliers innumerous applications of DSP, networking, etc.

Citations

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IJARIIE P. DIVYA, and E.C. RAMAKRISHNA. "FPGA Based 64X64 MAC Design Using Vedic Multiplier and DKG Adder" International Journal Of Advance Research And Innovative Ideas In Education Volume 4 Issue 4 2018 Page 757-762
MLA P. DIVYA, and E.C. RAMAKRISHNA. "FPGA Based 64X64 MAC Design Using Vedic Multiplier and DKG Adder." International Journal Of Advance Research And Innovative Ideas In Education 4.4(2018) : 757-762.
APA P. DIVYA, & E.C. RAMAKRISHNA. (2018). FPGA Based 64X64 MAC Design Using Vedic Multiplier and DKG Adder. International Journal Of Advance Research And Innovative Ideas In Education, 4(4), 757-762.
Chicago P. DIVYA, and E.C. RAMAKRISHNA. "FPGA Based 64X64 MAC Design Using Vedic Multiplier and DKG Adder." International Journal Of Advance Research And Innovative Ideas In Education 4, no. 4 (2018) : 757-762.
Oxford P. DIVYA, and E.C. RAMAKRISHNA. 'FPGA Based 64X64 MAC Design Using Vedic Multiplier and DKG Adder', International Journal Of Advance Research And Innovative Ideas In Education, vol. 4, no. 4, 2018, p. 757-762. Available from IJARIIE, http://ijariie.com/AdminUploadPdf/FPGA_Based_64X64_MAC_Design_Using_Vedic_Multiplier_and_DKG_Adder_ijariie8958.pdf (Accessed : 26 July 2018).
Harvard P. DIVYA, and E.C. RAMAKRISHNA. (2018) 'FPGA Based 64X64 MAC Design Using Vedic Multiplier and DKG Adder', International Journal Of Advance Research And Innovative Ideas In Education, 4(4), pp. 757-762IJARIIE [Online]. Available at: http://ijariie.com/AdminUploadPdf/FPGA_Based_64X64_MAC_Design_Using_Vedic_Multiplier_and_DKG_Adder_ijariie8958.pdf (Accessed : 26 July 2018)
IEEE P. DIVYA, and E.C. RAMAKRISHNA, "FPGA Based 64X64 MAC Design Using Vedic Multiplier and DKG Adder," International Journal Of Advance Research And Innovative Ideas In Education, vol. 4, no. 4, pp. 757-762, Jul-Aug 2018. [Online]. Available: http://ijariie.com/AdminUploadPdf/FPGA_Based_64X64_MAC_Design_Using_Vedic_Multiplier_and_DKG_Adder_ijariie8958.pdf [Accessed : 26 July 2018].
Turabian P. DIVYA, and E.C. RAMAKRISHNA. "FPGA Based 64X64 MAC Design Using Vedic Multiplier and DKG Adder." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 4 number 4 (26 July 2018).
Vancouver P. DIVYA, and E.C. RAMAKRISHNA. FPGA Based 64X64 MAC Design Using Vedic Multiplier and DKG Adder. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2018 [Cited : 26 July 2018]; 4(4) : 757-762. Available from: http://ijariie.com/AdminUploadPdf/FPGA_Based_64X64_MAC_Design_Using_Vedic_Multiplier_and_DKG_Adder_ijariie8958.pdf
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