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Title: :  DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES
PaperId: :  22849
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 10 Issue 2 2024
DUI:    16.0415/IJARIIE-22849
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
KALAVA YASWANTH REDDYVASIREDDY VENKATADRI INSTITUTE OF TECHNOLOGY
JORGIE LEELA MANOHARVASIREDDY VENKATADRI INSTITUTE OF TECHNOLOGY
PADAMATI SIDDHARDHAVASIREDDY VENKATADRI INSTITUTE OF TECHNOLOGY
NELAVALLI RAKESH CHOWDARYVASIREDDY VENKATADRI INSTITUTE OF TECHNOLOGY

Abstract

ELECTRONICS AND COMMUNICATION ENGINEERING
Reversible logic gate, Power dissipation, Time delay.
In this paper a 4x4 bit reversible multiplier circuit is proposed and designed. The proposed reversible multiplier is faster and has lower hardware complexity compared to the existing counterparts. Firstly, the Full Adder is Designed using Toffoli gates and then the certain number of Toffoli gates and the designed Full Adders are instantiated to design the reversible multiplier. Xilinx VIVADO simulations are carried out using parameters with a power supply voltage of 5V. The simulation results also confirm that proposed designs give better performance than conventional standard based design. It is also better than the existing counterparts in term of number of gates. Thus, this paper provides the comparison of two multipliers according to their number of gates required and number of constant inputs. The proposed reversible 4x4 multiplier circuit can be generalized for NxN bit multiplication.

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IJARIIE KALAVA YASWANTH REDDY, JORGIE LEELA MANOHAR, PADAMATI SIDDHARDHA, and NELAVALLI RAKESH CHOWDARY. "DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES" International Journal Of Advance Research And Innovative Ideas In Education Volume 10 Issue 2 2024 Page 924-931
MLA KALAVA YASWANTH REDDY, JORGIE LEELA MANOHAR, PADAMATI SIDDHARDHA, and NELAVALLI RAKESH CHOWDARY. "DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES." International Journal Of Advance Research And Innovative Ideas In Education 10.2(2024) : 924-931.
APA KALAVA YASWANTH REDDY, JORGIE LEELA MANOHAR, PADAMATI SIDDHARDHA, & NELAVALLI RAKESH CHOWDARY. (2024). DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES. International Journal Of Advance Research And Innovative Ideas In Education, 10(2), 924-931.
Chicago KALAVA YASWANTH REDDY, JORGIE LEELA MANOHAR, PADAMATI SIDDHARDHA, and NELAVALLI RAKESH CHOWDARY. "DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES." International Journal Of Advance Research And Innovative Ideas In Education 10, no. 2 (2024) : 924-931.
Oxford KALAVA YASWANTH REDDY, JORGIE LEELA MANOHAR, PADAMATI SIDDHARDHA, and NELAVALLI RAKESH CHOWDARY. 'DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES', International Journal Of Advance Research And Innovative Ideas In Education, vol. 10, no. 2, 2024, p. 924-931. Available from IJARIIE, http://ijariie.com/AdminUploadPdf/DEVELOPING_A_LOW_POWER_MULTIPLIER_UTILIZING_REVERSIBLE LOGIC GATES_ijariie22849.pdf (Accessed : ).
Harvard KALAVA YASWANTH REDDY, JORGIE LEELA MANOHAR, PADAMATI SIDDHARDHA, and NELAVALLI RAKESH CHOWDARY. (2024) 'DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES', International Journal Of Advance Research And Innovative Ideas In Education, 10(2), pp. 924-931IJARIIE [Online]. Available at: http://ijariie.com/AdminUploadPdf/DEVELOPING_A_LOW_POWER_MULTIPLIER_UTILIZING_REVERSIBLE LOGIC GATES_ijariie22849.pdf (Accessed : )
IEEE KALAVA YASWANTH REDDY, JORGIE LEELA MANOHAR, PADAMATI SIDDHARDHA, and NELAVALLI RAKESH CHOWDARY, "DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES," International Journal Of Advance Research And Innovative Ideas In Education, vol. 10, no. 2, pp. 924-931, Mar-App 2024. [Online]. Available: http://ijariie.com/AdminUploadPdf/DEVELOPING_A_LOW_POWER_MULTIPLIER_UTILIZING_REVERSIBLE LOGIC GATES_ijariie22849.pdf [Accessed : ].
Turabian KALAVA YASWANTH REDDY, JORGIE LEELA MANOHAR, PADAMATI SIDDHARDHA, and NELAVALLI RAKESH CHOWDARY. "DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 10 number 2 ().
Vancouver KALAVA YASWANTH REDDY, JORGIE LEELA MANOHAR, PADAMATI SIDDHARDHA, and NELAVALLI RAKESH CHOWDARY. DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2024 [Cited : ]; 10(2) : 924-931. Available from: http://ijariie.com/AdminUploadPdf/DEVELOPING_A_LOW_POWER_MULTIPLIER_UTILIZING_REVERSIBLE LOGIC GATES_ijariie22849.pdf
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