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Title: :  An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications
PaperId: :  23284
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 10 Issue 2 2024
DUI:    16.0415/IJARIIE-23284
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
E. Rama Krishna ReddyUsha Rama College of Engineering and Technology
R. TarunUsha Rama College of Engineering and Technology
Ch. Ashok KumarUsha Rama College of Engineering and Technology
M. Venkata RaoUsha Rama College of Engineering and Technology

Abstract

Electronics and Communication Engineering
4-bit array multiplier, adiabatic logic, low-power VLSI, Near Threshold Region, NTAL approach, TSMC 65 nm CMOS technology, mixer circuit, signal and image processing, energy efficiency, Tanner EDA, Spectre simulator, and power dissipation optimization
This research presents an innovative technique to designing a 4-bit array multiplier for mixer circuit applications in signal and image processing, based on an efficient low-power VLSI methodology. The suggested architecture uses adiabatic approaches in the Near Threshold Region to optimize the trade-off between propagation delay and power dissipation. Multipliers are essential components in many digital electronics contexts, resulting in the birth of many multiplier types customized to certain applications. This technology significantly reduces dynamic and static power dissipation as compared to traditional CMOS technologies. Near Threshold Adiabatic Logic (NTAL) is implemented using a single time-varying power source, which simplifies clock tree management and increases energy efficiency. The suggested design is simulated on the TSMC 65 nm technology node using the Tanner EDA tool and the Spectre simulator, guaranteeing that the optimized outcome is verified. Compared to typical CMOS approaches, while maintaining similar design parameters, there is a significant improvement in power dissipation of roughly 66.6%, 14.4%, and 64.6% for variable frequency, supply voltage, and load capacitance, respectively. Notably, with frequency variation, the load capacitance is held constant at Cload = 10 pF and VDD (max) = 1.2 V; with supply voltage variation, the load capacitance remains constant at Cload = 10 pF and frequency at F = 4 GHz; and with load capacitance variation, the frequency is maintained at F = 4 GHz and the supply voltage at VDD (max) = 1.2 V.

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IJARIIE E. Rama Krishna Reddy, R. Tarun, Ch. Ashok Kumar, and M. Venkata Rao. "An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications" International Journal Of Advance Research And Innovative Ideas In Education Volume 10 Issue 2 2024 Page 3711-3724
MLA E. Rama Krishna Reddy, R. Tarun, Ch. Ashok Kumar, and M. Venkata Rao. "An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications." International Journal Of Advance Research And Innovative Ideas In Education 10.2(2024) : 3711-3724.
APA E. Rama Krishna Reddy, R. Tarun, Ch. Ashok Kumar, & M. Venkata Rao. (2024). An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications. International Journal Of Advance Research And Innovative Ideas In Education, 10(2), 3711-3724.
Chicago E. Rama Krishna Reddy, R. Tarun, Ch. Ashok Kumar, and M. Venkata Rao. "An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications." International Journal Of Advance Research And Innovative Ideas In Education 10, no. 2 (2024) : 3711-3724.
Oxford E. Rama Krishna Reddy, R. Tarun, Ch. Ashok Kumar, and M. Venkata Rao. 'An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications', International Journal Of Advance Research And Innovative Ideas In Education, vol. 10, no. 2, 2024, p. 3711-3724. Available from IJARIIE, http://ijariie.com/AdminUploadPdf/An_Efficient_Adiabatic_4_Bit_Array_Multiplier_for_Low_Power_Applications_ijariie23284.pdf (Accessed : ).
Harvard E. Rama Krishna Reddy, R. Tarun, Ch. Ashok Kumar, and M. Venkata Rao. (2024) 'An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications', International Journal Of Advance Research And Innovative Ideas In Education, 10(2), pp. 3711-3724IJARIIE [Online]. Available at: http://ijariie.com/AdminUploadPdf/An_Efficient_Adiabatic_4_Bit_Array_Multiplier_for_Low_Power_Applications_ijariie23284.pdf (Accessed : )
IEEE E. Rama Krishna Reddy, R. Tarun, Ch. Ashok Kumar, and M. Venkata Rao, "An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications," International Journal Of Advance Research And Innovative Ideas In Education, vol. 10, no. 2, pp. 3711-3724, Mar-App 2024. [Online]. Available: http://ijariie.com/AdminUploadPdf/An_Efficient_Adiabatic_4_Bit_Array_Multiplier_for_Low_Power_Applications_ijariie23284.pdf [Accessed : ].
Turabian E. Rama Krishna Reddy, R. Tarun, Ch. Ashok Kumar, and M. Venkata Rao. "An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 10 number 2 ().
Vancouver E. Rama Krishna Reddy, R. Tarun, Ch. Ashok Kumar, and M. Venkata Rao. An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2024 [Cited : ]; 10(2) : 3711-3724. Available from: http://ijariie.com/AdminUploadPdf/An_Efficient_Adiabatic_4_Bit_Array_Multiplier_for_Low_Power_Applications_ijariie23284.pdf
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