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Title: :  High Speed Low-Power Gate Level Synchronous Full Adder Designs
PaperId: :  26621
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 11 Issue 3 2025
DUI:    16.0415/IJARIIE-26621
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
sreenivasa RSJM Institute of Technology,Chitradurga
Dr.Siddesh K BSJM Institute of Technology,Chitradurga
Prof.Chetan SSJM Institute of Technology,Chitradurga
Vinay M SSJM Institute of Technology,Chitradurga
Gagan H RSJM Institute of Technology,Chitradurga
Manjunatha TSJM Institute of Technology,Chitradurga

Abstract

Electronics and Communication Engineering
Full Adder Design Gate-Level Design Synchronous Circuits Low Power VLSI High Speed Adders XNM Architecture XAC Full Adder XNAIMC Design Transistor Optimization Power-Delay Product (PDP) Digital Circuit Design CMOS Logic Arithmetic Logic Unit (ALU) Tanner EDA Area Efficient Adder Multiplexer-Based Adder XNOR-Based Logic Signal Integrity Logic-Level Optimization VLSI Architecture
In modern VLSI design, the full adder remains a fundamental component, directly influencing the overall efficiency of arithmetic circuits. This paper presents novel high-speed gate-level synchronous full adder designs that significantly optimize critical performance parameters including area, delay, and power consumption. Existing full adder implementations using AND-OR logic, half adders, and 2:1 multiplexers exhibit higher transistor counts (up to 74), increased delay (up to 20.03 ns), and elevated power dissipation (up to 137.5 µW). In contrast, the proposed designs—XAC, XNM, and XNAIMC—demonstrate remarkable improvements. The XNM design achieves the lowest delay of 0.032 ns and minimal power consumption of 0.335 µW with a reduced transistor count of 37. The XAC variant further reduces area to just 34 transistors, while maintaining efficient performance. These results confirm the effectiveness of the proposed architectures in advancing low-power, high-speed digital circuit design, making them highly suitable for next-generation VLSI systems.

Citations

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IJARIIE sreenivasa R, Dr.Siddesh K B, Prof.Chetan S, Vinay M S, Gagan H R, and Manjunatha T. "High Speed Low-Power Gate Level Synchronous Full Adder Designs" International Journal Of Advance Research And Innovative Ideas In Education Volume 11 Issue 3 2025 Page 1483-1489
MLA sreenivasa R, Dr.Siddesh K B, Prof.Chetan S, Vinay M S, Gagan H R, and Manjunatha T. "High Speed Low-Power Gate Level Synchronous Full Adder Designs." International Journal Of Advance Research And Innovative Ideas In Education 11.3(2025) : 1483-1489.
APA sreenivasa R, Dr.Siddesh K B, Prof.Chetan S, Vinay M S, Gagan H R, & Manjunatha T. (2025). High Speed Low-Power Gate Level Synchronous Full Adder Designs. International Journal Of Advance Research And Innovative Ideas In Education, 11(3), 1483-1489.
Chicago sreenivasa R, Dr.Siddesh K B, Prof.Chetan S, Vinay M S, Gagan H R, and Manjunatha T. "High Speed Low-Power Gate Level Synchronous Full Adder Designs." International Journal Of Advance Research And Innovative Ideas In Education 11, no. 3 (2025) : 1483-1489.
Oxford sreenivasa R, Dr.Siddesh K B, Prof.Chetan S, Vinay M S, Gagan H R, and Manjunatha T. 'High Speed Low-Power Gate Level Synchronous Full Adder Designs', International Journal Of Advance Research And Innovative Ideas In Education, vol. 11, no. 3, 2025, p. 1483-1489. Available from IJARIIE, http://ijariie.com/AdminUploadPdf/High_Speed_Low_Power_Gate_Level_Synchronous_Full_Adder_Designs_ijariie26621.pdf (Accessed : ).
Harvard sreenivasa R, Dr.Siddesh K B, Prof.Chetan S, Vinay M S, Gagan H R, and Manjunatha T. (2025) 'High Speed Low-Power Gate Level Synchronous Full Adder Designs', International Journal Of Advance Research And Innovative Ideas In Education, 11(3), pp. 1483-1489IJARIIE [Online]. Available at: http://ijariie.com/AdminUploadPdf/High_Speed_Low_Power_Gate_Level_Synchronous_Full_Adder_Designs_ijariie26621.pdf (Accessed : )
IEEE sreenivasa R, Dr.Siddesh K B, Prof.Chetan S, Vinay M S, Gagan H R, and Manjunatha T, "High Speed Low-Power Gate Level Synchronous Full Adder Designs," International Journal Of Advance Research And Innovative Ideas In Education, vol. 11, no. 3, pp. 1483-1489, May-Jun 2025. [Online]. Available: http://ijariie.com/AdminUploadPdf/High_Speed_Low_Power_Gate_Level_Synchronous_Full_Adder_Designs_ijariie26621.pdf [Accessed : ].
Turabian sreenivasa R, Dr.Siddesh K B, Prof.Chetan S, Vinay M S, Gagan H R, and Manjunatha T. "High Speed Low-Power Gate Level Synchronous Full Adder Designs." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 11 number 3 ().
Vancouver sreenivasa R, Dr.Siddesh K B, Prof.Chetan S, Vinay M S, Gagan H R, and Manjunatha T. High Speed Low-Power Gate Level Synchronous Full Adder Designs. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2025 [Cited : ]; 11(3) : 1483-1489. Available from: http://ijariie.com/AdminUploadPdf/High_Speed_Low_Power_Gate_Level_Synchronous_Full_Adder_Designs_ijariie26621.pdf
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