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Title: :  Design, Simulation, and Layout of a Folded Cascode Operational Amplifier in 180 nm CMOS Technology
PaperId: :  26977
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 11 Issue 3 2025
DUI:    16.0415/IJARIIE-26977
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
Nguyen Thi Hai NinhThai Nguyen University of Technology
Dang Thi Ngoc AnhThai Nguyen University of Technology

Abstract

Electronics Engineering
CMOS Op-Amp, Folded Cascode, Analog Design, PSpice Simulation, Cadence
This paper presents the design approach and theoretical foundation for developing a folded cascode operational amplifier (op-amp) using 180nm CMOS technology. The folded cascode architecture is widely recognized for its ability to provide high gain and wide output swing in a single-stage amplifier configuration, making it a compelling choice for low-power, high-performance analog front-end circuits. Its inherent advantages in voltage headroom, frequency response, and noise performance have positioned it as a preferred topology in many integrated analog systems. The primary objective of this study is to explore the full design flow of a folded cascode op-amp, from theoretical analysis to schematic implementation and physical layout. The design methodology emphasizes proper transistor sizing, current biasing, and compensation strategies that contribute to stable operation and predictable frequency behavior. Attention is given to matching techniques, layout symmetry, and parasitic reduction, all of which are crucial for ensuring high precision and manufacturability in submicron CMOS processes. In addition to the design steps, the paper discusses the rationale behind architectural decisions, trade-offs involved in single-stage design, and key layout considerations that impact analog performance. The focus remains on demonstrating a structured and educationally grounded design process that can serve as a practical reference for students and early-career engineers working in analog IC design. This approach not only reinforces analog design principles but also encourages methodical thinking aligned with industry practices.

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IJARIIE Nguyen Thi Hai Ninh, and Dang Thi Ngoc Anh. "Design, Simulation, and Layout of a Folded Cascode Operational Amplifier in 180 nm CMOS Technology" International Journal Of Advance Research And Innovative Ideas In Education Volume 11 Issue 3 2025 Page 4182-4187
MLA Nguyen Thi Hai Ninh, and Dang Thi Ngoc Anh. "Design, Simulation, and Layout of a Folded Cascode Operational Amplifier in 180 nm CMOS Technology." International Journal Of Advance Research And Innovative Ideas In Education 11.3(2025) : 4182-4187.
APA Nguyen Thi Hai Ninh, & Dang Thi Ngoc Anh. (2025). Design, Simulation, and Layout of a Folded Cascode Operational Amplifier in 180 nm CMOS Technology. International Journal Of Advance Research And Innovative Ideas In Education, 11(3), 4182-4187.
Chicago Nguyen Thi Hai Ninh, and Dang Thi Ngoc Anh. "Design, Simulation, and Layout of a Folded Cascode Operational Amplifier in 180 nm CMOS Technology." International Journal Of Advance Research And Innovative Ideas In Education 11, no. 3 (2025) : 4182-4187.
Oxford Nguyen Thi Hai Ninh, and Dang Thi Ngoc Anh. 'Design, Simulation, and Layout of a Folded Cascode Operational Amplifier in 180 nm CMOS Technology', International Journal Of Advance Research And Innovative Ideas In Education, vol. 11, no. 3, 2025, p. 4182-4187. Available from IJARIIE, http://ijariie.com/AdminUploadPdf/Design__Simulation__and_Layout_of_a_Folded_Cascode_Operational_Amplifier_in_180 nm_CMOS_Technology_ijariie26977.pdf (Accessed : 03 July 2025).
Harvard Nguyen Thi Hai Ninh, and Dang Thi Ngoc Anh. (2025) 'Design, Simulation, and Layout of a Folded Cascode Operational Amplifier in 180 nm CMOS Technology', International Journal Of Advance Research And Innovative Ideas In Education, 11(3), pp. 4182-4187IJARIIE [Online]. Available at: http://ijariie.com/AdminUploadPdf/Design__Simulation__and_Layout_of_a_Folded_Cascode_Operational_Amplifier_in_180 nm_CMOS_Technology_ijariie26977.pdf (Accessed : 03 July 2025)
IEEE Nguyen Thi Hai Ninh, and Dang Thi Ngoc Anh, "Design, Simulation, and Layout of a Folded Cascode Operational Amplifier in 180 nm CMOS Technology," International Journal Of Advance Research And Innovative Ideas In Education, vol. 11, no. 3, pp. 4182-4187, May-Jun 2025. [Online]. Available: http://ijariie.com/AdminUploadPdf/Design__Simulation__and_Layout_of_a_Folded_Cascode_Operational_Amplifier_in_180 nm_CMOS_Technology_ijariie26977.pdf [Accessed : 03 July 2025].
Turabian Nguyen Thi Hai Ninh, and Dang Thi Ngoc Anh. "Design, Simulation, and Layout of a Folded Cascode Operational Amplifier in 180 nm CMOS Technology." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 11 number 3 (03 July 2025).
Vancouver Nguyen Thi Hai Ninh, and Dang Thi Ngoc Anh. Design, Simulation, and Layout of a Folded Cascode Operational Amplifier in 180 nm CMOS Technology. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2025 [Cited : 03 July 2025]; 11(3) : 4182-4187. Available from: http://ijariie.com/AdminUploadPdf/Design__Simulation__and_Layout_of_a_Folded_Cascode_Operational_Amplifier_in_180 nm_CMOS_Technology_ijariie26977.pdf
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