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Title: :  FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD
PaperId: :  4073
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 3 Issue 2 2017
DUI:    16.0415/IJARIIE-4073
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
Ms.C.KowsalyaKathir College of Engineering
Mrs.S.KalaivaniKathir College of Engineering

Abstract

Power Electronics and Drives
IGBT, Gate drivers, Multilevel inverter, Hybrid level, MATLAB/SIMULINK.
Application of multilevel inverters for higher voltage goals in industries has become more popular. In this study, new structures for symmetric, asymmetric and hybrid multilevel inverter are recommended. The proposed structure is used in high-voltage levels. The proposed structure can generate a great number of voltage levels with minimum number of power electronic components such as Insulated Gate Bipolar Transistors (IGBT) and gate drivers. For proposed asymmetric and hybrid inverter, new methods for determination of DC voltage sources values are presented. Comparison of the results of various multilevel inverters is presented to reflect the merits of the recommended structures. The operations of the proposed multilevel inverter structures are verified with the experimental and simulation results of an asymmetric 31-level. Fundamental frequency-switching method is applied to the new topologies to trigger the power switches for controlling the voltage levels generated on the output. Verification of the analytical results is performed using MATLAB/SIMULINK software.

Citations

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IJARIIE Ms.C.Kowsalya, and Mrs.S.Kalaivani. "FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD" International Journal Of Advance Research And Innovative Ideas In Education Volume 3 Issue 2 2017 Page 651-658
MLA Ms.C.Kowsalya, and Mrs.S.Kalaivani. "FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD." International Journal Of Advance Research And Innovative Ideas In Education 3.2(2017) : 651-658.
APA Ms.C.Kowsalya, & Mrs.S.Kalaivani. (2017). FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD. International Journal Of Advance Research And Innovative Ideas In Education, 3(2), 651-658.
Chicago Ms.C.Kowsalya, and Mrs.S.Kalaivani. "FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD." International Journal Of Advance Research And Innovative Ideas In Education 3, no. 2 (2017) : 651-658.
Oxford Ms.C.Kowsalya, and Mrs.S.Kalaivani. 'FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD', International Journal Of Advance Research And Innovative Ideas In Education, vol. 3, no. 2, 2017, p. 651-658. Available from IJARIIE, http://ijariie.com/AdminUploadPdf/FPGA_based_implementation_of_new_hybrid_configuration_31_level_inverter_with_reduced_number_of_switches_for_reduced_THD_ijariie4073.pdf (Accessed : 26 January 2021).
Harvard Ms.C.Kowsalya, and Mrs.S.Kalaivani. (2017) 'FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD', International Journal Of Advance Research And Innovative Ideas In Education, 3(2), pp. 651-658IJARIIE [Online]. Available at: http://ijariie.com/AdminUploadPdf/FPGA_based_implementation_of_new_hybrid_configuration_31_level_inverter_with_reduced_number_of_switches_for_reduced_THD_ijariie4073.pdf (Accessed : 26 January 2021)
IEEE Ms.C.Kowsalya, and Mrs.S.Kalaivani, "FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD," International Journal Of Advance Research And Innovative Ideas In Education, vol. 3, no. 2, pp. 651-658, Mar-App 2017. [Online]. Available: http://ijariie.com/AdminUploadPdf/FPGA_based_implementation_of_new_hybrid_configuration_31_level_inverter_with_reduced_number_of_switches_for_reduced_THD_ijariie4073.pdf [Accessed : 26 January 2021].
Turabian Ms.C.Kowsalya, and Mrs.S.Kalaivani. "FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 3 number 2 (26 January 2021).
Vancouver Ms.C.Kowsalya, and Mrs.S.Kalaivani. FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2017 [Cited : 26 January 2021]; 3(2) : 651-658. Available from: http://ijariie.com/AdminUploadPdf/FPGA_based_implementation_of_new_hybrid_configuration_31_level_inverter_with_reduced_number_of_switches_for_reduced_THD_ijariie4073.pdf
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