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Call for Papers:Vol.11 Issue.3

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Title: :  DESIGN OF SINGLE CYCLE RISC-V PROCESSOR
PaperId: :  22774
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 10 Issue 2 2024
DUI:    16.0415/IJARIIE-22774
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
Talluri PriyaVasireddy Venkatadri Institute of Technology
Paruchuri UshasriVasireddy Venkatadri Institute of Technology
Vetagiri Bhuvana JyothirmaiVasireddy Venkatadri Institute of Technology

Abstract

VLSI design
RISC-V (Reduced instruction set computer 5th generation), Single cycle processor, Instruction Set Architecture (ISA), Data path, control unit
In the early the computer was stack architecture, later replaced by RISC architecture. The RISC-V Processor features a streamlined set of instructions, a consistent instruction length, an increased number of general-purpose registers, a load-store architecture, and simplified addressing modes. These characteristics contribute to faster execution of individual instructions, leading to improved overall performance and a simplified design. The choice of a RISC is easily understood. The processor is designed for targeting low-cost embedded devices. A Single-Cycle RISC-V Processor is a simplified, yet highly efficient microprocessor architecture that executes instructions in a single clock cycle. This design philosophy emphasizes minimalism, reduced complexity, and enhanced pipelining, which leads to faster execution times and a streamlined hardware structure. By implementing a RISC-V architecture, the processor benefits from an open standard, making it ideal for customization, expansion, and adaptation to various computing applications. The design of a Single-Cycle RISC-V Processor represents a significant leap in microprocessor architecture. Its minimalist design, open-source RISC-V instruction set, and single-cycle execution offer efficiency, scalability, and adaptability, making it an ideal choice for modern computing systems.

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IJARIIE Talluri Priya, Paruchuri Ushasri, and Vetagiri Bhuvana Jyothirmai. "DESIGN OF SINGLE CYCLE RISC-V PROCESSOR" International Journal Of Advance Research And Innovative Ideas In Education Volume 10 Issue 2 2024 Page 527-533
MLA Talluri Priya, Paruchuri Ushasri, and Vetagiri Bhuvana Jyothirmai. "DESIGN OF SINGLE CYCLE RISC-V PROCESSOR." International Journal Of Advance Research And Innovative Ideas In Education 10.2(2024) : 527-533.
APA Talluri Priya, Paruchuri Ushasri, & Vetagiri Bhuvana Jyothirmai. (2024). DESIGN OF SINGLE CYCLE RISC-V PROCESSOR. International Journal Of Advance Research And Innovative Ideas In Education, 10(2), 527-533.
Chicago Talluri Priya, Paruchuri Ushasri, and Vetagiri Bhuvana Jyothirmai. "DESIGN OF SINGLE CYCLE RISC-V PROCESSOR." International Journal Of Advance Research And Innovative Ideas In Education 10, no. 2 (2024) : 527-533.
Oxford Talluri Priya, Paruchuri Ushasri, and Vetagiri Bhuvana Jyothirmai. 'DESIGN OF SINGLE CYCLE RISC-V PROCESSOR', International Journal Of Advance Research And Innovative Ideas In Education, vol. 10, no. 2, 2024, p. 527-533. Available from IJARIIE, https://ijariie.com/AdminUploadPdf/DESIGN_OF_SINGLE_CYCLE_RISC_V_PROCESSOR_ijariie22774.pdf (Accessed : 11 March 2025).
Harvard Talluri Priya, Paruchuri Ushasri, and Vetagiri Bhuvana Jyothirmai. (2024) 'DESIGN OF SINGLE CYCLE RISC-V PROCESSOR', International Journal Of Advance Research And Innovative Ideas In Education, 10(2), pp. 527-533IJARIIE [Online]. Available at: https://ijariie.com/AdminUploadPdf/DESIGN_OF_SINGLE_CYCLE_RISC_V_PROCESSOR_ijariie22774.pdf (Accessed : 11 March 2025)
IEEE Talluri Priya, Paruchuri Ushasri, and Vetagiri Bhuvana Jyothirmai, "DESIGN OF SINGLE CYCLE RISC-V PROCESSOR," International Journal Of Advance Research And Innovative Ideas In Education, vol. 10, no. 2, pp. 527-533, Mar-App 2024. [Online]. Available: https://ijariie.com/AdminUploadPdf/DESIGN_OF_SINGLE_CYCLE_RISC_V_PROCESSOR_ijariie22774.pdf [Accessed : 11 March 2025].
Turabian Talluri Priya, Paruchuri Ushasri, and Vetagiri Bhuvana Jyothirmai. "DESIGN OF SINGLE CYCLE RISC-V PROCESSOR." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 10 number 2 (11 March 2025).
Vancouver Talluri Priya, Paruchuri Ushasri, and Vetagiri Bhuvana Jyothirmai. DESIGN OF SINGLE CYCLE RISC-V PROCESSOR. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2024 [Cited : 11 March 2025]; 10(2) : 527-533. Available from: https://ijariie.com/AdminUploadPdf/DESIGN_OF_SINGLE_CYCLE_RISC_V_PROCESSOR_ijariie22774.pdf
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