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Title: :  Speed Efficient 64 Bit MAC Design using VEDIC Multiplier and Reversible Logic Gates
PaperId: :  6937
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 3 Issue 6 2017
DUI:    16.0415/IJARIIE-6937
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
K.Aruna SreeINTELL ENGINEERING COLLEGE
S.T.MrudulaINTELL ENGINEERING COLLEGE
K.GeethaINTELL ENGINEERING COLLEGE
R.RamachandraINTELL ENGINEERING COLLEGE

Abstract

electronics and communication engineering
PPG, PPA, MAC, DSP
A multiplying block operate may be concededin 3 totally different ways: standard addition, partial product addition (PPA) and eventually partial product Generation (PPG).The two bud vase materials that must be considered are raising the speed of MAC which is accumulator block partial and product reduction. The 64 bit MAC design which will make use of Vedic multiplier and reversible logic gate can be accomplished in two stages. Firstly, multiplier stage, where a usual multiplier is replaced by Vedic multiplier using UrdhavaTriyagbhayam sutra from Vedic Mathematics. Multiplication is the primary operation of MAC unit. Speed, area, Power dissipation, consumption and latency are the major concerns in the multiplier stage. So, to evade them, we are going to select quick multipliers innumerous applications of DSP, networking, etc.

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IJARIIE K.Aruna Sree, S.T.Mrudula, K.Geetha, and R.Ramachandra. "Speed Efficient 64 Bit MAC Design using VEDIC Multiplier and Reversible Logic Gates" International Journal Of Advance Research And Innovative Ideas In Education Volume 3 Issue 6 2017 Page 370-376
MLA K.Aruna Sree, S.T.Mrudula, K.Geetha, and R.Ramachandra. "Speed Efficient 64 Bit MAC Design using VEDIC Multiplier and Reversible Logic Gates." International Journal Of Advance Research And Innovative Ideas In Education 3.6(2017) : 370-376.
APA K.Aruna Sree, S.T.Mrudula, K.Geetha, & R.Ramachandra. (2017). Speed Efficient 64 Bit MAC Design using VEDIC Multiplier and Reversible Logic Gates. International Journal Of Advance Research And Innovative Ideas In Education, 3(6), 370-376.
Chicago K.Aruna Sree, S.T.Mrudula, K.Geetha, and R.Ramachandra. "Speed Efficient 64 Bit MAC Design using VEDIC Multiplier and Reversible Logic Gates." International Journal Of Advance Research And Innovative Ideas In Education 3, no. 6 (2017) : 370-376.
Oxford K.Aruna Sree, S.T.Mrudula, K.Geetha, and R.Ramachandra. 'Speed Efficient 64 Bit MAC Design using VEDIC Multiplier and Reversible Logic Gates', International Journal Of Advance Research And Innovative Ideas In Education, vol. 3, no. 6, 2017, p. 370-376. Available from IJARIIE, https://ijariie.com/AdminUploadPdf/Speed_Efficient_64_Bit_MAC_Design_using_VEDIC_Multiplier_and_Reversible_Logic_Gates_ijariie6937.pdf (Accessed : ).
Harvard K.Aruna Sree, S.T.Mrudula, K.Geetha, and R.Ramachandra. (2017) 'Speed Efficient 64 Bit MAC Design using VEDIC Multiplier and Reversible Logic Gates', International Journal Of Advance Research And Innovative Ideas In Education, 3(6), pp. 370-376IJARIIE [Online]. Available at: https://ijariie.com/AdminUploadPdf/Speed_Efficient_64_Bit_MAC_Design_using_VEDIC_Multiplier_and_Reversible_Logic_Gates_ijariie6937.pdf (Accessed : )
IEEE K.Aruna Sree, S.T.Mrudula, K.Geetha, and R.Ramachandra, "Speed Efficient 64 Bit MAC Design using VEDIC Multiplier and Reversible Logic Gates," International Journal Of Advance Research And Innovative Ideas In Education, vol. 3, no. 6, pp. 370-376, Nov-Dec 2017. [Online]. Available: https://ijariie.com/AdminUploadPdf/Speed_Efficient_64_Bit_MAC_Design_using_VEDIC_Multiplier_and_Reversible_Logic_Gates_ijariie6937.pdf [Accessed : ].
Turabian K.Aruna Sree, S.T.Mrudula, K.Geetha, and R.Ramachandra. "Speed Efficient 64 Bit MAC Design using VEDIC Multiplier and Reversible Logic Gates." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 3 number 6 ().
Vancouver K.Aruna Sree, S.T.Mrudula, K.Geetha, and R.Ramachandra. Speed Efficient 64 Bit MAC Design using VEDIC Multiplier and Reversible Logic Gates. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2017 [Cited : ]; 3(6) : 370-376. Available from: https://ijariie.com/AdminUploadPdf/Speed_Efficient_64_Bit_MAC_Design_using_VEDIC_Multiplier_and_Reversible_Logic_Gates_ijariie6937.pdf
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