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Title: :  Performance Analysis of different MUX for FPGA
PaperId: :  2070
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 2 Issue 3 2016
DUI:    16.0415/IJARIIE-2070
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
Prof. S. M.Turkane PREC Loni,
N.V.Ambedkar PREC Loni,
S.V.Kaname PREC Loni,
T.V.Kharde PREC Loni,

Abstract

Electronics and Telecommunication
CMOS, LUT, 2:1Multiplexer, 4:1Multiplexer, 8:1 Multiplexer.
A Field-Programmable Gate Array is an FPD featuring a general structure that permits very high logic capacity. FPGAs offer higher ratio of flip-flops to logic resources than do CPLDs. The main problem is power dissipation than speed and area. In this paper, the primary and important issue within the low power MOSFET circuit is power dissipation. The methods we use for reducing power and energy dissipation in conventional CMOS circuit comprise reducing the power supply voltages and the nodes, capacitances or switch activities with efficient charge recovery logic. This paper also determine with multiplexer to improve the ability and design a 2:1, 4:1 and 8:1 multiplexer with CMOS transistor. All the results of this paper are simulated on SYMICA tool realized in 22nm and 32nm technology.

Citations

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IJARIIE Prof. S. M.Turkane, N.V.Ambedkar, S.V.Kaname, and T.V.Kharde. "Performance Analysis of different MUX for FPGA" International Journal Of Advance Research And Innovative Ideas In Education Volume 2 Issue 3 2016 Page 87-93
MLA Prof. S. M.Turkane, N.V.Ambedkar, S.V.Kaname, and T.V.Kharde. "Performance Analysis of different MUX for FPGA." International Journal Of Advance Research And Innovative Ideas In Education 2.3(2016) : 87-93.
APA Prof. S. M.Turkane, N.V.Ambedkar, S.V.Kaname, & T.V.Kharde. (2016). Performance Analysis of different MUX for FPGA. International Journal Of Advance Research And Innovative Ideas In Education, 2(3), 87-93.
Chicago Prof. S. M.Turkane, N.V.Ambedkar, S.V.Kaname, and T.V.Kharde. "Performance Analysis of different MUX for FPGA." International Journal Of Advance Research And Innovative Ideas In Education 2, no. 3 (2016) : 87-93.
Oxford Prof. S. M.Turkane, N.V.Ambedkar, S.V.Kaname, and T.V.Kharde. 'Performance Analysis of different MUX for FPGA', International Journal Of Advance Research And Innovative Ideas In Education, vol. 2, no. 3, 2016, p. 87-93. Available from IJARIIE, https://ijariie.com/AdminUploadPdf/Performance_Analysis_of_different_MUX_for_FPGA_ijariie2070.pdf (Accessed : ).
Harvard Prof. S. M.Turkane, N.V.Ambedkar, S.V.Kaname, and T.V.Kharde. (2016) 'Performance Analysis of different MUX for FPGA', International Journal Of Advance Research And Innovative Ideas In Education, 2(3), pp. 87-93IJARIIE [Online]. Available at: https://ijariie.com/AdminUploadPdf/Performance_Analysis_of_different_MUX_for_FPGA_ijariie2070.pdf (Accessed : )
IEEE Prof. S. M.Turkane, N.V.Ambedkar, S.V.Kaname, and T.V.Kharde, "Performance Analysis of different MUX for FPGA," International Journal Of Advance Research And Innovative Ideas In Education, vol. 2, no. 3, pp. 87-93, May-Jun 2016. [Online]. Available: https://ijariie.com/AdminUploadPdf/Performance_Analysis_of_different_MUX_for_FPGA_ijariie2070.pdf [Accessed : ].
Turabian Prof. S. M.Turkane, N.V.Ambedkar, S.V.Kaname, and T.V.Kharde. "Performance Analysis of different MUX for FPGA." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 2 number 3 ().
Vancouver Prof. S. M.Turkane, N.V.Ambedkar, S.V.Kaname, and T.V.Kharde. Performance Analysis of different MUX for FPGA. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2016 [Cited : ]; 2(3) : 87-93. Available from: https://ijariie.com/AdminUploadPdf/Performance_Analysis_of_different_MUX_for_FPGA_ijariie2070.pdf
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