Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit
Abstract & Details
Research Area
Electronics and communication
Keywords
CMOS
Lector
Sleep
Stack
Sleepy Stack
nMOS
pMOS
DualStack
Low power consumption
delay
Abstract
With shrinking technology, power management is becoming an important factor for almost every design
and application. The key challenges in deep sub micrometer technology are reducing the power
consumption and overall power management on the chip. At the very early stage power management
needs to be considered. Also at every design stage low-power techniques should to be employed, from
RTL to GDSII. This paper describes various techniques for low power VLSI circuits. Future challenges
that must be met with designers is to design low power high performance circuits.
License
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Commons
Attribution-ShareAlike 4.0 International License.
Author Information
| # | Name | Institute / Affiliation |
|---|---|---|
| 1 | Rahul Itnal | Alvas institute of engineering and technology |
| 2 | Rakshitha Rao | Alvas institute of engineering and technology |
| 3 | Rashmi Rao | Alvas institute of engineering and technology |
| 4 | Shraddha | Alvas institute of engineering and technology |
| 5 | Praveen J | Alvas institute of engineering and technology |
How to Cite
Use the following formats to cite this article in your research.
APA Style
Itnal, Rahul, Rao, Rakshitha, Rao, Rashmi, Shraddha, & J, Praveen (2019). Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit. International Journal of Advance Research and Innovative Ideas In Education, 5(2), 2214-2220.
MLA Style
Itnal, Rahul, et al. "Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit." International Journal of Advance Research and Innovative Ideas In Education, vol. 5, no. 2, 2019, pp. 2214-2220.
IEEE Style
Rahul Itnal, Rakshitha Rao, Rashmi Rao, Shraddha, and Praveen J, "Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit," International Journal of Advance Research and Innovative Ideas In Education, vol. 5, no. 2, pp. 2214-2220, 2019.
Vancouver Style
Itnal Rahul, Rao Rakshitha, Rao Rashmi, Shraddha, J Praveen. Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit. International Journal of Advance Research and Innovative Ideas In Education. 2019;5(2):2214-2220.
Harvard Style
Itnal, Rahul, Rao, Rakshitha, Rao, Rashmi, Shraddha, & J, Praveen (2019) 'Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit', International Journal of Advance Research and Innovative Ideas In Education, 5(2), pp. 2214-2220.
Chicago Style
Itnal, Rahul, et al. "Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit." International Journal of Advance Research and Innovative Ideas In Education 5, no. 2 (2019): 2214-2220.
Turabian Style
Itnal, Rahul, et al. "Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit." International Journal of Advance Research and Innovative Ideas In Education 5, no. 2 (2019): 2214-2220.