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Title: :  ANALYSIS, DESIGN & IMPLEMENTATION OF LOW POWER 10T FULL ADDER CIRCUIT
PaperId: :  13151
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 6 Issue 6 2020
DUI:    16.0415/IJARIIE-13151
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
VIJAY KUMAR SHARMABHABHA UNIVERSITY
Prof. Suresh GawandeBhabha University

Abstract

Electronics Engineering
Full Adder, CMOS, DSCH, MICROWIND, Transmission Gate Logic
Full adder is the heart of any central processing unit that is a core component employed in all the processors. This paper presents a design methodology for full adder circuit with minimum number of transistor i.e. reduced size & reduced area. This is then used to implement 10T full adder design for carrying out summation of bits. The analysis of the developed full adder design is done at room temperature CMOS 90 nm and 180 nm technologies using Micro wind tool 2.6.The result shows the comparison between different CMOS technologies in 90 nm and 180 nm using micro wind tool 2.6 on the design in regards of power dissipation, propagation delay and power delay product. A comparison table shown having power, delay and transistor count based comparison at 90 nm and 180 nm technologies showing delay in time and dissipated Power within the full adder summation circuit design at room temperatures. We will also provide the layout of the full adder design at both technologies. The proposed technique shows 96.66% less power consumption in 90 nm and 93.93% less power consumption in 180nm as compare to base paper hybrid logic design.

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IJARIIE VIJAY KUMAR SHARMA, and Prof. Suresh Gawande. "ANALYSIS, DESIGN & IMPLEMENTATION OF LOW POWER 10T FULL ADDER CIRCUIT" International Journal Of Advance Research And Innovative Ideas In Education Volume 6 Issue 6 2020 Page 685-694
MLA VIJAY KUMAR SHARMA, and Prof. Suresh Gawande. "ANALYSIS, DESIGN & IMPLEMENTATION OF LOW POWER 10T FULL ADDER CIRCUIT." International Journal Of Advance Research And Innovative Ideas In Education 6.6(2020) : 685-694.
APA VIJAY KUMAR SHARMA, & Prof. Suresh Gawande. (2020). ANALYSIS, DESIGN & IMPLEMENTATION OF LOW POWER 10T FULL ADDER CIRCUIT. International Journal Of Advance Research And Innovative Ideas In Education, 6(6), 685-694.
Chicago VIJAY KUMAR SHARMA, and Prof. Suresh Gawande. "ANALYSIS, DESIGN & IMPLEMENTATION OF LOW POWER 10T FULL ADDER CIRCUIT." International Journal Of Advance Research And Innovative Ideas In Education 6, no. 6 (2020) : 685-694.
Oxford VIJAY KUMAR SHARMA, and Prof. Suresh Gawande. 'ANALYSIS, DESIGN & IMPLEMENTATION OF LOW POWER 10T FULL ADDER CIRCUIT', International Journal Of Advance Research And Innovative Ideas In Education, vol. 6, no. 6, 2020, p. 685-694. Available from IJARIIE, http://ijariie.com/AdminUploadPdf/ANALYSIS__DESIGN___IMPLEMENTATION_OF_LOW_POWER_10T_FULL_ADDER_CIRCUIT_ijariie13151.pdf (Accessed : 29 November 2020).
Harvard VIJAY KUMAR SHARMA, and Prof. Suresh Gawande. (2020) 'ANALYSIS, DESIGN & IMPLEMENTATION OF LOW POWER 10T FULL ADDER CIRCUIT', International Journal Of Advance Research And Innovative Ideas In Education, 6(6), pp. 685-694IJARIIE [Online]. Available at: http://ijariie.com/AdminUploadPdf/ANALYSIS__DESIGN___IMPLEMENTATION_OF_LOW_POWER_10T_FULL_ADDER_CIRCUIT_ijariie13151.pdf (Accessed : 29 November 2020)
IEEE VIJAY KUMAR SHARMA, and Prof. Suresh Gawande, "ANALYSIS, DESIGN & IMPLEMENTATION OF LOW POWER 10T FULL ADDER CIRCUIT," International Journal Of Advance Research And Innovative Ideas In Education, vol. 6, no. 6, pp. 685-694, Nov-Dec 2020. [Online]. Available: http://ijariie.com/AdminUploadPdf/ANALYSIS__DESIGN___IMPLEMENTATION_OF_LOW_POWER_10T_FULL_ADDER_CIRCUIT_ijariie13151.pdf [Accessed : 29 November 2020].
Turabian VIJAY KUMAR SHARMA, and Prof. Suresh Gawande. "ANALYSIS, DESIGN & IMPLEMENTATION OF LOW POWER 10T FULL ADDER CIRCUIT." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 6 number 6 (29 November 2020).
Vancouver VIJAY KUMAR SHARMA, and Prof. Suresh Gawande. ANALYSIS, DESIGN & IMPLEMENTATION OF LOW POWER 10T FULL ADDER CIRCUIT. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2020 [Cited : 29 November 2020]; 6(6) : 685-694. Available from: http://ijariie.com/AdminUploadPdf/ANALYSIS__DESIGN___IMPLEMENTATION_OF_LOW_POWER_10T_FULL_ADDER_CIRCUIT_ijariie13151.pdf
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