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Title: :  MULTIPLE CELL UPSET TOLERANT ERROR DETECTION AND CORRECTION CODE FOR SEMICONDUCTOR MEMORIES USING DSSC
PaperId: :  9692
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 5 Issue 2 2019
DUI:    16.0415/IJARIIE-9692
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
BEULA SHARON MPRINCE SHRI VENKATESHWARA PADMAVATHY ENGINEERING COLLEGE
GULHAAR SPRINCE SHRI VENKATESHWARA PADMAVATHY ENGINEERING COLLEGE

Abstract

Electronics Communication engineering
Data segmentation ,cell upsets, correction codes
The presented project presents the implementation and evaluation of the Data Segmentation Section Code (DSSC), a new algorithm for the detection and correction of multiple transient faults in volatile memories with low cost implementation. DSSC is an ECC based on two-dimensional (2D) codes, that aims to correct and detect MCUs in memories The proposal in split the data bits in three regions was elaborated in order to select a specific group of bit to operate the correction process. By calculating parity and diagonal check bits and syndrome bits the errors are detected and corrected region wise .This approach reduces considerably the area and power cost. Our proposed system has been coded in Verilog HDL and simulated using Xilinx 12.1

Citations

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IJARIIE BEULA SHARON M, and GULHAAR S. "MULTIPLE CELL UPSET TOLERANT ERROR DETECTION AND CORRECTION CODE FOR SEMICONDUCTOR MEMORIES USING DSSC" International Journal Of Advance Research And Innovative Ideas In Education Volume 5 Issue 2 2019 Page 625-628
MLA BEULA SHARON M, and GULHAAR S. "MULTIPLE CELL UPSET TOLERANT ERROR DETECTION AND CORRECTION CODE FOR SEMICONDUCTOR MEMORIES USING DSSC." International Journal Of Advance Research And Innovative Ideas In Education 5.2(2019) : 625-628.
APA BEULA SHARON M, & GULHAAR S. (2019). MULTIPLE CELL UPSET TOLERANT ERROR DETECTION AND CORRECTION CODE FOR SEMICONDUCTOR MEMORIES USING DSSC. International Journal Of Advance Research And Innovative Ideas In Education, 5(2), 625-628.
Chicago BEULA SHARON M, and GULHAAR S. "MULTIPLE CELL UPSET TOLERANT ERROR DETECTION AND CORRECTION CODE FOR SEMICONDUCTOR MEMORIES USING DSSC." International Journal Of Advance Research And Innovative Ideas In Education 5, no. 2 (2019) : 625-628.
Oxford BEULA SHARON M, and GULHAAR S. 'MULTIPLE CELL UPSET TOLERANT ERROR DETECTION AND CORRECTION CODE FOR SEMICONDUCTOR MEMORIES USING DSSC', International Journal Of Advance Research And Innovative Ideas In Education, vol. 5, no. 2, 2019, p. 625-628. Available from IJARIIE, https://ijariie.com/AdminUploadPdf/MULTIPLE_CELL_UPSET_TOLERANT_ERROR_DETECTION_AND_CORRECTION_CODE_FOR_SEMICONDUCTOR_MEMORIES_USING_DSSC_ijariie9692.pdf (Accessed : ).
Harvard BEULA SHARON M, and GULHAAR S. (2019) 'MULTIPLE CELL UPSET TOLERANT ERROR DETECTION AND CORRECTION CODE FOR SEMICONDUCTOR MEMORIES USING DSSC', International Journal Of Advance Research And Innovative Ideas In Education, 5(2), pp. 625-628IJARIIE [Online]. Available at: https://ijariie.com/AdminUploadPdf/MULTIPLE_CELL_UPSET_TOLERANT_ERROR_DETECTION_AND_CORRECTION_CODE_FOR_SEMICONDUCTOR_MEMORIES_USING_DSSC_ijariie9692.pdf (Accessed : )
IEEE BEULA SHARON M, and GULHAAR S, "MULTIPLE CELL UPSET TOLERANT ERROR DETECTION AND CORRECTION CODE FOR SEMICONDUCTOR MEMORIES USING DSSC," International Journal Of Advance Research And Innovative Ideas In Education, vol. 5, no. 2, pp. 625-628, Mar-App 2019. [Online]. Available: https://ijariie.com/AdminUploadPdf/MULTIPLE_CELL_UPSET_TOLERANT_ERROR_DETECTION_AND_CORRECTION_CODE_FOR_SEMICONDUCTOR_MEMORIES_USING_DSSC_ijariie9692.pdf [Accessed : ].
Turabian BEULA SHARON M, and GULHAAR S. "MULTIPLE CELL UPSET TOLERANT ERROR DETECTION AND CORRECTION CODE FOR SEMICONDUCTOR MEMORIES USING DSSC." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 5 number 2 ().
Vancouver BEULA SHARON M, and GULHAAR S. MULTIPLE CELL UPSET TOLERANT ERROR DETECTION AND CORRECTION CODE FOR SEMICONDUCTOR MEMORIES USING DSSC. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2019 [Cited : ]; 5(2) : 625-628. Available from: https://ijariie.com/AdminUploadPdf/MULTIPLE_CELL_UPSET_TOLERANT_ERROR_DETECTION_AND_CORRECTION_CODE_FOR_SEMICONDUCTOR_MEMORIES_USING_DSSC_ijariie9692.pdf
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