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Call for Papers:Vol.11 Issue.4

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Title: :  Advance Techniques for Lower Power Digital VLSI
PaperId: :  13448
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 4 Issue 2 2018
DUI:    16.0415/IJARIIE-13448
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
Divya KanugantiResearch Scholar of Sri Satya Sai University
Dr. Anil KumarResearch Supervisor of Sri Satya Sai University

Abstract

Electronics
Power, Digital, VLSI, Semiconductor, PMOS, NMOS.
The principle point of this examination is to talk about the Lower Power Digital VLSI Using High Speed SRAM, To improve the plan limitations: strength, speed, spillage current and postpone which impacts the presentation of SRAM cell and besides presents the various procedures, find better arrangement through Simulation done on different SRAM cell, explore the Low Power SRAM Cell geographies on 65 nm development by using various boundaries and to assess the usage of MTCMOS Technique on Conventional and Ground–Gated SRAM cell geographies. The principle objective of our own will be keeping up execution of psyche cell continuously activity. The working of SRAM will be impacted by extraneous and inherent boundaries. Now, we'll be focusing on essential 3 boundaries: dependability, spillage current and deferral.

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IJARIIE Divya Kanuganti, and Dr. Anil Kumar. "Advance Techniques for Lower Power Digital VLSI" International Journal Of Advance Research And Innovative Ideas In Education Volume 4 Issue 2 2018 Page 4934-4938
MLA Divya Kanuganti, and Dr. Anil Kumar. "Advance Techniques for Lower Power Digital VLSI." International Journal Of Advance Research And Innovative Ideas In Education 4.2(2018) : 4934-4938.
APA Divya Kanuganti, & Dr. Anil Kumar. (2018). Advance Techniques for Lower Power Digital VLSI. International Journal Of Advance Research And Innovative Ideas In Education, 4(2), 4934-4938.
Chicago Divya Kanuganti, and Dr. Anil Kumar. "Advance Techniques for Lower Power Digital VLSI." International Journal Of Advance Research And Innovative Ideas In Education 4, no. 2 (2018) : 4934-4938.
Oxford Divya Kanuganti, and Dr. Anil Kumar. 'Advance Techniques for Lower Power Digital VLSI', International Journal Of Advance Research And Innovative Ideas In Education, vol. 4, no. 2, 2018, p. 4934-4938. Available from IJARIIE, https://ijariie.com/AdminUploadPdf/Advance_Techniques_for_Lower_Power_Digital_VLSI_ijariie13448.pdf (Accessed : 10 February 2021).
Harvard Divya Kanuganti, and Dr. Anil Kumar. (2018) 'Advance Techniques for Lower Power Digital VLSI', International Journal Of Advance Research And Innovative Ideas In Education, 4(2), pp. 4934-4938IJARIIE [Online]. Available at: https://ijariie.com/AdminUploadPdf/Advance_Techniques_for_Lower_Power_Digital_VLSI_ijariie13448.pdf (Accessed : 10 February 2021)
IEEE Divya Kanuganti, and Dr. Anil Kumar, "Advance Techniques for Lower Power Digital VLSI," International Journal Of Advance Research And Innovative Ideas In Education, vol. 4, no. 2, pp. 4934-4938, Mar-App 2018. [Online]. Available: https://ijariie.com/AdminUploadPdf/Advance_Techniques_for_Lower_Power_Digital_VLSI_ijariie13448.pdf [Accessed : 10 February 2021].
Turabian Divya Kanuganti, and Dr. Anil Kumar. "Advance Techniques for Lower Power Digital VLSI." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 4 number 2 (10 February 2021).
Vancouver Divya Kanuganti, and Dr. Anil Kumar. Advance Techniques for Lower Power Digital VLSI. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2018 [Cited : 10 February 2021]; 4(2) : 4934-4938. Available from: https://ijariie.com/AdminUploadPdf/Advance_Techniques_for_Lower_Power_Digital_VLSI_ijariie13448.pdf
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