MULTIPLE CELL UPSET TOLERANT ERROR DETECTION AND CORRECTION CODE FOR SEMICONDUCTOR MEMORIES USING DSSC

Electronics Communication engineering

The presented project presents the implementation and evaluation of the Data Segmentation Section Code (DSSC), a new algorithm for the detection and correction of multiple transient faults in volatile memories with low cost implementation. DSSC is an ECC based on two-dimensional (2D) codes, that aims to correct and detect MCUs in memories The proposal in split the data bits in three regions was elaborated in order to select a specific group of bit to operate the correction process. By calculating parity and diagonal check bits and syndrome bits the errors are detected and corrected region wise .This approach reduces considerably the area and power cost. Our proposed system has been coded in Verilog HDL and simulated using Xilinx 12.1

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