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Title: :  Device design Methodology to optimize low frequency noise in SOI Technology
PaperId: :  1577
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 2 Issue 1 2016
DUI:    16.0415/IJARIIE-1577
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
Prem Prakash SatpathyCIT Ranchi
Dr. Vijay NathBIT Mesra
Mr. Abhinandan JainPratap University

Abstract

Silicon on Insulator
Floating body effect, SOI, kink effect, edge effect
Device design methodology for SOI is to improve power and reduce low frequency noise generated randomly. An effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. SOI introduces one of the greatest future generation technologies of this decade. Silicon-on-Insulator transistors are fabricated in a small ~100 nm layer of silicon, located on top of a silicon dioxide layer, called buried oxide. This oxide layer provides full dielectric isolation of the transistor and thus most of the parasitic effects present in bulk silicon transistors are eliminated. The structure of the SOI transistor is depicted and is very similar to that of the bulk transistor. The main difference is the presence of the buried oxide it provides attractive properties to the SOI transistor. Power has become one of the most important paradigms of design convergence for multi gigahertz communication such as optical data links wireless products and microprocessor ASIC or SOC designs. Power consumption has become bottleneck in microprocessor design.

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IJARIIE Prem Prakash Satpathy, Dr. Vijay Nath, and Mr. Abhinandan Jain. "Device design Methodology to optimize low frequency noise in SOI Technology" International Journal Of Advance Research And Innovative Ideas In Education Volume 2 Issue 1 2016 Page 298-302
MLA Prem Prakash Satpathy, Dr. Vijay Nath, and Mr. Abhinandan Jain. "Device design Methodology to optimize low frequency noise in SOI Technology." International Journal Of Advance Research And Innovative Ideas In Education 2.1(2016) : 298-302.
APA Prem Prakash Satpathy, Dr. Vijay Nath, & Mr. Abhinandan Jain. (2016). Device design Methodology to optimize low frequency noise in SOI Technology. International Journal Of Advance Research And Innovative Ideas In Education, 2(1), 298-302.
Chicago Prem Prakash Satpathy, Dr. Vijay Nath, and Mr. Abhinandan Jain. "Device design Methodology to optimize low frequency noise in SOI Technology." International Journal Of Advance Research And Innovative Ideas In Education 2, no. 1 (2016) : 298-302.
Oxford Prem Prakash Satpathy, Dr. Vijay Nath, and Mr. Abhinandan Jain. 'Device design Methodology to optimize low frequency noise in SOI Technology', International Journal Of Advance Research And Innovative Ideas In Education, vol. 2, no. 1, 2016, p. 298-302. Available from IJARIIE, http://ijariie.com/AdminUploadPdf/Device_design_Methodology_to_optimize_low__frequency_noise_in_SOI_Technology_ijariie1577.pdf (Accessed : ).
Harvard Prem Prakash Satpathy, Dr. Vijay Nath, and Mr. Abhinandan Jain. (2016) 'Device design Methodology to optimize low frequency noise in SOI Technology', International Journal Of Advance Research And Innovative Ideas In Education, 2(1), pp. 298-302IJARIIE [Online]. Available at: http://ijariie.com/AdminUploadPdf/Device_design_Methodology_to_optimize_low__frequency_noise_in_SOI_Technology_ijariie1577.pdf (Accessed : )
IEEE Prem Prakash Satpathy, Dr. Vijay Nath, and Mr. Abhinandan Jain, "Device design Methodology to optimize low frequency noise in SOI Technology," International Journal Of Advance Research And Innovative Ideas In Education, vol. 2, no. 1, pp. 298-302, Jan-Feb 2016. [Online]. Available: http://ijariie.com/AdminUploadPdf/Device_design_Methodology_to_optimize_low__frequency_noise_in_SOI_Technology_ijariie1577.pdf [Accessed : ].
Turabian Prem Prakash Satpathy, Dr. Vijay Nath, and Mr. Abhinandan Jain. "Device design Methodology to optimize low frequency noise in SOI Technology." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 2 number 1 ().
Vancouver Prem Prakash Satpathy, Dr. Vijay Nath, and Mr. Abhinandan Jain. Device design Methodology to optimize low frequency noise in SOI Technology. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2016 [Cited : ]; 2(1) : 298-302. Available from: http://ijariie.com/AdminUploadPdf/Device_design_Methodology_to_optimize_low__frequency_noise_in_SOI_Technology_ijariie1577.pdf
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