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Title: :  IMPLEMENTATION of DEEP NEURAL NETWORK ACCELERATOR USING FPGA
PaperId: :  18163
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 8 Issue 5 2022
DUI:    16.0415/IJARIIE-18163
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
S PradeepMiracle Educational Society Group of Institutions
P. SrideviMiracle Educational Society Group of Institutions
N Seshu KumarMiracle Educational Society Group of Institutions
P. JyostnaMiracle Educational Society Group of Institutions

Abstract

Electronics and Communication Engineering
Field programmable gate arrays, Neural network hardware, Fixed-point arithmetic, 2D convolution, Digital arithmetic
Low-precision arithmetic operations to accelerate deep-learning applications on field- programmable gate arrays (FPGAs) have been studied extensively, because they offer the potential to save silicon area. However, these benefits come at the cost of a decrease in accuracy. Neural network-based methods for image processing are becoming widely used in practical applications. Modern neural networks are computationally expensive and require specialized hardware, such as graphics processing units. Since such hardware is not always available in real life applications, there is a compelling need for the design of neural networks for mobile devices. Mobile neural networks typically have reduced number of parameters and require a relatively small number of arithmetic operations. However, they usually still are executed at the software level and use floating-point calculations. The use of mobile networks without further optimization may not provide sufficient performance when high processing speed is required, for example, in real-time video processing (30 frames per second). In this study, we suggest optimizations to speed up computations in order to efficiently use already trained neural networks on a mobile device.

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IJARIIE S Pradeep, P. Sridevi, N Seshu Kumar, and P. Jyostna. "IMPLEMENTATION of DEEP NEURAL NETWORK ACCELERATOR USING FPGA" International Journal Of Advance Research And Innovative Ideas In Education Volume 8 Issue 5 2022 Page 332-340
MLA S Pradeep, P. Sridevi, N Seshu Kumar, and P. Jyostna. "IMPLEMENTATION of DEEP NEURAL NETWORK ACCELERATOR USING FPGA." International Journal Of Advance Research And Innovative Ideas In Education 8.5(2022) : 332-340.
APA S Pradeep, P. Sridevi, N Seshu Kumar, & P. Jyostna. (2022). IMPLEMENTATION of DEEP NEURAL NETWORK ACCELERATOR USING FPGA. International Journal Of Advance Research And Innovative Ideas In Education, 8(5), 332-340.
Chicago S Pradeep, P. Sridevi, N Seshu Kumar, and P. Jyostna. "IMPLEMENTATION of DEEP NEURAL NETWORK ACCELERATOR USING FPGA." International Journal Of Advance Research And Innovative Ideas In Education 8, no. 5 (2022) : 332-340.
Oxford S Pradeep, P. Sridevi, N Seshu Kumar, and P. Jyostna. 'IMPLEMENTATION of DEEP NEURAL NETWORK ACCELERATOR USING FPGA', International Journal Of Advance Research And Innovative Ideas In Education, vol. 8, no. 5, 2022, p. 332-340. Available from IJARIIE, https://ijariie.com/AdminUploadPdf/IMPLEMENTATION_of_DEEP_NEURAL_NETWORK_ACCELERATOR_USING_FPGA_ijariie18163.pdf (Accessed : ).
Harvard S Pradeep, P. Sridevi, N Seshu Kumar, and P. Jyostna. (2022) 'IMPLEMENTATION of DEEP NEURAL NETWORK ACCELERATOR USING FPGA', International Journal Of Advance Research And Innovative Ideas In Education, 8(5), pp. 332-340IJARIIE [Online]. Available at: https://ijariie.com/AdminUploadPdf/IMPLEMENTATION_of_DEEP_NEURAL_NETWORK_ACCELERATOR_USING_FPGA_ijariie18163.pdf (Accessed : )
IEEE S Pradeep, P. Sridevi, N Seshu Kumar, and P. Jyostna, "IMPLEMENTATION of DEEP NEURAL NETWORK ACCELERATOR USING FPGA," International Journal Of Advance Research And Innovative Ideas In Education, vol. 8, no. 5, pp. 332-340, Sep-Oct 2022. [Online]. Available: https://ijariie.com/AdminUploadPdf/IMPLEMENTATION_of_DEEP_NEURAL_NETWORK_ACCELERATOR_USING_FPGA_ijariie18163.pdf [Accessed : ].
Turabian S Pradeep, P. Sridevi, N Seshu Kumar, and P. Jyostna. "IMPLEMENTATION of DEEP NEURAL NETWORK ACCELERATOR USING FPGA." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 8 number 5 ().
Vancouver S Pradeep, P. Sridevi, N Seshu Kumar, and P. Jyostna. IMPLEMENTATION of DEEP NEURAL NETWORK ACCELERATOR USING FPGA. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2022 [Cited : ]; 8(5) : 332-340. Available from: https://ijariie.com/AdminUploadPdf/IMPLEMENTATION_of_DEEP_NEURAL_NETWORK_ACCELERATOR_USING_FPGA_ijariie18163.pdf
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