Call for Papers:Vol.9 Issue.2

Submission
Last date		 30-Apr-2023
Acceptance Status In One Day
Paper Publish In Two Days
Submit ManuScript

News & Updates

Submit Article

Dear Authors, Article publish in our journal for Volume-9,Issue-2. For article submission on below link: Submit Manuscript


Join As Board

Dear Reviewer, You can join our Reviewer team without given any charges in our journal. Submit Details on below link: Join As Board


Paper Publication Charges

IJARIIE APP
Download Android App

For Authors

Archives

IJARIIE Board

Downloads

Android App

Download IJARIIE APP

Authors

Title: :  " WATCHDOG TIMER USING VHDL FOR ATM SYSTEM "
PaperId: :  1846
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 2 Issue 2 2016
DUI:    16.0415/IJARIIE-1846
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
Mr.Gore Shukracharya Sampatti MCOERC-Nashik, Maharashtra, India
Lokhande Abhijit AshokMCOERC-Nashik, Maharashtra, India
Mahajan Sachin BapuMCOERC-Nashik, Maharashtra, India

Abstract

Electronics and Telecommunication Engineering ( VLSI-System)
ATM (Automated Teller Machine), CLB(Configurable Logic Blocks), DLL (Delay Locked Loops ), DRC (Design Rule Checker), EMI (Electromagnetic Interference), FPGA(Field Programmable Gate Array),VHDL (Very High Speed Integrated Circuits Hardware Description Language ), VLSI ( Very Large Scale Integration).
A watchdog timer is a computer hardware timing device that triggers a system reset if the main program, due to some fault condition, such as a hang, neglects to regularly service the watchdog. The intention is to bring the system back from the hung state into normal operation. Such a timer has got various important applications, one of them being in ATMs which we have studied in our paper. We can implement watchdog timer by using hardware as well as software. The advantage of implement it using software rather than hardware is that it will required less power consumption, less cost and we obtain high speed compare to hardware. The compatible or good known language for Xilinx is VHDL. The key advantage of VHDL when used for systems design is that it allows the behavior of the required system to be described (modeled) and verified (simulated) before synthesis tools translate the design into real hardware (gates and wires) and information theory. The simulation tool that we have used is Xilinx 6.2i . Xilinx provide platform for VHDL. First the required code for timer circuit was written in VHDL and simulated so as to obtain the required output waveforms. After the coding was completed, VHDL model is translated into the "gates and wires" that are mapped onto a programmable logic device. The programmable logic device used here is Spartan-II. The above coding and burning methods were completed and the output was observed on FPGA kit. The timer code was implemented using VHDL while burning was done using Spartan-II kit.

Citations

Copy and paste a formatted citation or use one of the links to import into a bibliography manager and reference.

IJARIIE Mr.Gore Shukracharya Sampatti , Lokhande Abhijit Ashok, and Mahajan Sachin Bapu. "" WATCHDOG TIMER USING VHDL FOR ATM SYSTEM "" International Journal Of Advance Research And Innovative Ideas In Education Volume 2 Issue 2 2016 Page 873-877
MLA Mr.Gore Shukracharya Sampatti , Lokhande Abhijit Ashok, and Mahajan Sachin Bapu. "" WATCHDOG TIMER USING VHDL FOR ATM SYSTEM "." International Journal Of Advance Research And Innovative Ideas In Education 2.2(2016) : 873-877.
APA Mr.Gore Shukracharya Sampatti , Lokhande Abhijit Ashok, & Mahajan Sachin Bapu. (2016). " WATCHDOG TIMER USING VHDL FOR ATM SYSTEM ". International Journal Of Advance Research And Innovative Ideas In Education, 2(2), 873-877.
Chicago Mr.Gore Shukracharya Sampatti , Lokhande Abhijit Ashok, and Mahajan Sachin Bapu. "" WATCHDOG TIMER USING VHDL FOR ATM SYSTEM "." International Journal Of Advance Research And Innovative Ideas In Education 2, no. 2 (2016) : 873-877.
Oxford Mr.Gore Shukracharya Sampatti , Lokhande Abhijit Ashok, and Mahajan Sachin Bapu. '" WATCHDOG TIMER USING VHDL FOR ATM SYSTEM "', International Journal Of Advance Research And Innovative Ideas In Education, vol. 2, no. 2, 2016, p. 873-877. Available from IJARIIE, http://ijariie.com/AdminUploadPdf/__WATCHDOG_TIMER_USING_VHDL_FOR_ATM_SYSTEM___ijariie1846.pdf (Accessed : 18 March 2019).
Harvard Mr.Gore Shukracharya Sampatti , Lokhande Abhijit Ashok, and Mahajan Sachin Bapu. (2016) '" WATCHDOG TIMER USING VHDL FOR ATM SYSTEM "', International Journal Of Advance Research And Innovative Ideas In Education, 2(2), pp. 873-877IJARIIE [Online]. Available at: http://ijariie.com/AdminUploadPdf/__WATCHDOG_TIMER_USING_VHDL_FOR_ATM_SYSTEM___ijariie1846.pdf (Accessed : 18 March 2019)
IEEE Mr.Gore Shukracharya Sampatti , Lokhande Abhijit Ashok, and Mahajan Sachin Bapu, "" WATCHDOG TIMER USING VHDL FOR ATM SYSTEM "," International Journal Of Advance Research And Innovative Ideas In Education, vol. 2, no. 2, pp. 873-877, Mar-App 2016. [Online]. Available: http://ijariie.com/AdminUploadPdf/__WATCHDOG_TIMER_USING_VHDL_FOR_ATM_SYSTEM___ijariie1846.pdf [Accessed : 18 March 2019].
Turabian Mr.Gore Shukracharya Sampatti , Lokhande Abhijit Ashok, and Mahajan Sachin Bapu. "" WATCHDOG TIMER USING VHDL FOR ATM SYSTEM "." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 2 number 2 (18 March 2019).
Vancouver Mr.Gore Shukracharya Sampatti , Lokhande Abhijit Ashok, and Mahajan Sachin Bapu. " WATCHDOG TIMER USING VHDL FOR ATM SYSTEM ". International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2016 [Cited : 18 March 2019]; 2(2) : 873-877. Available from: http://ijariie.com/AdminUploadPdf/__WATCHDOG_TIMER_USING_VHDL_FOR_ATM_SYSTEM___ijariie1846.pdf
BibTex EndNote RefMan RefWorks

Number Of Downloads


Last download on 3/18/2019 9:56:12 PM

Save in Google Drive

Similar-Paper

TitleArea of ResearchAuther NameAction
ASIC Implementation Of PULP RISC-V CoreElectronics and Communication EngineeringAnirudh Rao M Download
FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERSElectronics and Communication EngineeringShankar R Download
Metastability Mitigation & Error Masking of Flip-FlopElectronics & CommunicationAPARNA Download
DESIGN OF CURRENT STARVED VCO USING POWER GATED INVERTER FOR PLLElectronics & Communication EngineeringMEENAKSHI TIWARI Download
LVDS Design for High speed ApplicationElectronicsAtharvan Boxey Download
virtual paintig through gesture detection and color segmentation technique using DE2 FPGA boardElctronics and telecommunication engineeringMs. Pooja Bcahhav Download
Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuitElectronics and communicationRahul Itnal Download
THRESHOLD LOGIC’S IMPORTANCE IN BUILDING EFFICIENT AND COMPACT DIGITAL CIRCUITS AND ITS SCOPE IN MODERN TECHNOLOGYELECTRONICS AND COMMUNICATION ENGINEERINGE.VENU BHAGIRATH Download
A Review on Dysarthria speech disorderelectonics and telecommunicationYogita S. Mahadik Download
FUNCTIONAL VERIFICATION OF USB 2.0 VIP USING SV- UVMELECTRONICS & TELECOMMUNICATIONKAMINI JHA Download
Implementation of IEC 61131-3 Standard Compatible instruction List Processor on FPGA PlatformVLSI designSagar Shedge Download
SPEED AND AREA EFFICIENT VLSI ARCHITECTURES FOR MPSK MODEMSELECTRONICS AND COMMUNICATION ENGINEERINGESTHER RANI C Download
180nm CMOS process based L-band CML to CMOS converterElectronics and CommunicationChirag Senjalliya Download
DESIGN OF A MODULAR FEEDFORWARD PHASE/FREQUENCY DETECTOR FOR HIGH SPEED PLLVLSI Design & Embedded SystemRaju Patel Download
IMPROVING TEST COVERAGE OF SCL USING TEST POINT INSERTIONVLSI DESIGNSRUTHI M S Download
12