Call for Papers:Vol.11 Issue.4

Submission
Last date		 28-Aug-2025
Acceptance Status In One Day
Paper Publish In Two Days
Submit ManuScript

News & Updates

Submit Article

Dear Authors, Article publish in our journal for Volume-11,Issue-4. For article submission on below link: Submit Manuscript


Join As Board

Dear Reviewer, You can join our Reviewer team without given any charges in our journal. Submit Details on below link: Join As Board


Paper Publication Charges

IJARIIE APP
Download Android App

For Authors

Archives

IJARIIE Board

Downloads

Android App

Download IJARIIE APP

Authors

Title: :  An Approach to FinFET USING Ternary logic
PaperId: :  2173
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 2 Issue 3 2016
DUI:    16.0415/IJARIIE-2173
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
Kushawaha Jyoti DineshkumarGtu Pg School, Ahmedabad, Gujarat
Abhinav SinghVeltech Technical University, Chennai
Bhavit RathoreVeltech Technical University, Chennai

Abstract

VLSI System Design
FinFET, CMOS, ALU, Ternary logic.
Ternary Logic is advantageous choice to substitute binary logic as it is energy efficient and due to easiness, as interconnect and chip area are reduced. As CMOS technology is scaling down to nanometer regime there are many problems occurring such as short channel effect, DIBL and Hot electron Effect, these problems can be overcomed by replacing traditional CMOS by FinFET. These two methodologies are of great advantage and can result in new turn in nanoelectronics. Many circuits can be build up by using FinFET working on ternary logic rather than binary and the main is ALU as it is the heart of CPU. So designing circuits by these two methodologies has a great impact on upcoming technologies.

Citations

Copy and paste a formatted citation or use one of the links to import into a bibliography manager and reference.

IJARIIE Kushawaha Jyoti Dineshkumar, Abhinav Singh, and Bhavit Rathore. "An Approach to FinFET USING Ternary logic" International Journal Of Advance Research And Innovative Ideas In Education Volume 2 Issue 3 2016 Page 421-425
MLA Kushawaha Jyoti Dineshkumar, Abhinav Singh, and Bhavit Rathore. "An Approach to FinFET USING Ternary logic." International Journal Of Advance Research And Innovative Ideas In Education 2.3(2016) : 421-425.
APA Kushawaha Jyoti Dineshkumar, Abhinav Singh, & Bhavit Rathore. (2016). An Approach to FinFET USING Ternary logic. International Journal Of Advance Research And Innovative Ideas In Education, 2(3), 421-425.
Chicago Kushawaha Jyoti Dineshkumar, Abhinav Singh, and Bhavit Rathore. "An Approach to FinFET USING Ternary logic." International Journal Of Advance Research And Innovative Ideas In Education 2, no. 3 (2016) : 421-425.
Oxford Kushawaha Jyoti Dineshkumar, Abhinav Singh, and Bhavit Rathore. 'An Approach to FinFET USING Ternary logic', International Journal Of Advance Research And Innovative Ideas In Education, vol. 2, no. 3, 2016, p. 421-425. Available from IJARIIE, https://ijariie.com/AdminUploadPdf/An_Approach_to_FinFET_USING_Ternary__logic_ijariie2173.pdf (Accessed : 27 June 2019).
Harvard Kushawaha Jyoti Dineshkumar, Abhinav Singh, and Bhavit Rathore. (2016) 'An Approach to FinFET USING Ternary logic', International Journal Of Advance Research And Innovative Ideas In Education, 2(3), pp. 421-425IJARIIE [Online]. Available at: https://ijariie.com/AdminUploadPdf/An_Approach_to_FinFET_USING_Ternary__logic_ijariie2173.pdf (Accessed : 27 June 2019)
IEEE Kushawaha Jyoti Dineshkumar, Abhinav Singh, and Bhavit Rathore, "An Approach to FinFET USING Ternary logic," International Journal Of Advance Research And Innovative Ideas In Education, vol. 2, no. 3, pp. 421-425, May-Jun 2016. [Online]. Available: https://ijariie.com/AdminUploadPdf/An_Approach_to_FinFET_USING_Ternary__logic_ijariie2173.pdf [Accessed : 27 June 2019].
Turabian Kushawaha Jyoti Dineshkumar, Abhinav Singh, and Bhavit Rathore. "An Approach to FinFET USING Ternary logic." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 2 number 3 (27 June 2019).
Vancouver Kushawaha Jyoti Dineshkumar, Abhinav Singh, and Bhavit Rathore. An Approach to FinFET USING Ternary logic. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2016 [Cited : 27 June 2019]; 2(3) : 421-425. Available from: https://ijariie.com/AdminUploadPdf/An_Approach_to_FinFET_USING_Ternary__logic_ijariie2173.pdf
BibTex EndNote RefMan RefWorks

Number Of Downloads


Last download on 6/27/2019 4:54:56 AM

Save in Google Drive

Similar-Paper

TitleArea of ResearchAuther NameAction
Design Analysis and Implementation of Two Stage Operational AmplifierElectronics and Communication EngineeringRAJ KESARWANI Download
1X3 ROUTER RTL & UVM TESTBENCHElectronic and Telecommunication (VLSI BASED)MOHARIL ABOLI Download
ASIC Implementation Of PULP RISC-V CoreElectronics and Communication EngineeringAnirudh Rao M Download
FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERSElectronics and Communication EngineeringShankar R Download
Metastability Mitigation & Error Masking of Flip-FlopElectronics & CommunicationAPARNA Download
DESIGN OF CURRENT STARVED VCO USING POWER GATED INVERTER FOR PLLElectronics & Communication EngineeringMEENAKSHI TIWARI Download
LVDS Design for High speed ApplicationElectronicsAtharvan Boxey Download
virtual paintig through gesture detection and color segmentation technique using DE2 FPGA boardElctronics and telecommunication engineeringMs. Pooja Bcahhav Download
Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuitElectronics and communicationRahul Itnal Download
THRESHOLD LOGIC’S IMPORTANCE IN BUILDING EFFICIENT AND COMPACT DIGITAL CIRCUITS AND ITS SCOPE IN MODERN TECHNOLOGYELECTRONICS AND COMMUNICATION ENGINEERINGE.VENU BHAGIRATH Download
A Review on Dysarthria speech disorderelectonics and telecommunicationYogita S. Mahadik Download
FUNCTIONAL VERIFICATION OF USB 2.0 VIP USING SV- UVMELECTRONICS & TELECOMMUNICATIONKAMINI JHA Download
Implementation of IEC 61131-3 Standard Compatible instruction List Processor on FPGA PlatformVLSI designSagar Shedge Download
SPEED AND AREA EFFICIENT VLSI ARCHITECTURES FOR MPSK MODEMSELECTRONICS AND COMMUNICATION ENGINEERINGESTHER RANI C Download
180nm CMOS process based L-band CML to CMOS converterElectronics and CommunicationChirag Senjalliya Download
12