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Title: :  Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit
PaperId: :  10018
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 5 Issue 2 2019
DUI:    16.0415/IJARIIE-10018
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
Rahul ItnalAlvas institute of engineering and technology
Rakshitha RaoAlvas institute of engineering and technology
Rashmi RaoAlvas institute of engineering and technology
ShraddhaAlvas institute of engineering and technology
Praveen JAlvas institute of engineering and technology

Abstract

Electronics and communication
CMOS, Lector, Sleep, Stack, Sleepy Stack, nMOS, pMOS, DualStack, Low power consumption, delay
With shrinking technology, power management is becoming an important factor for almost every design and application. The key challenges in deep sub micrometer technology are reducing the power consumption and overall power management on the chip. At the very early stage power management needs to be considered. Also at every design stage low-power techniques should to be employed, from RTL to GDSII. This paper describes various techniques for low power VLSI circuits. Future challenges that must be met with designers is to design low power high performance circuits.

Citations

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IJARIIE Rahul Itnal, Rakshitha Rao, Rashmi Rao, Shraddha, and Praveen J. "Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit" International Journal Of Advance Research And Innovative Ideas In Education Volume 5 Issue 2 2019 Page 2214-2220
MLA Rahul Itnal, Rakshitha Rao, Rashmi Rao, Shraddha, and Praveen J. "Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit." International Journal Of Advance Research And Innovative Ideas In Education 5.2(2019) : 2214-2220.
APA Rahul Itnal, Rakshitha Rao, Rashmi Rao, Shraddha, & Praveen J. (2019). Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit. International Journal Of Advance Research And Innovative Ideas In Education, 5(2), 2214-2220.
Chicago Rahul Itnal, Rakshitha Rao, Rashmi Rao, Shraddha, and Praveen J. "Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit." International Journal Of Advance Research And Innovative Ideas In Education 5, no. 2 (2019) : 2214-2220.
Oxford Rahul Itnal, Rakshitha Rao, Rashmi Rao, Shraddha, and Praveen J. 'Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit', International Journal Of Advance Research And Innovative Ideas In Education, vol. 5, no. 2, 2019, p. 2214-2220. Available from IJARIIE, https://ijariie.com/AdminUploadPdf/Design_and_implementation_of_enhanced_sleepy_stack_with_LECTOR_technique_for_low_power_consumption_in_CMOS_VLSI_circuit_ijariie10018.pdf (Accessed : 14 July 2023).
Harvard Rahul Itnal, Rakshitha Rao, Rashmi Rao, Shraddha, and Praveen J. (2019) 'Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit', International Journal Of Advance Research And Innovative Ideas In Education, 5(2), pp. 2214-2220IJARIIE [Online]. Available at: https://ijariie.com/AdminUploadPdf/Design_and_implementation_of_enhanced_sleepy_stack_with_LECTOR_technique_for_low_power_consumption_in_CMOS_VLSI_circuit_ijariie10018.pdf (Accessed : 14 July 2023)
IEEE Rahul Itnal, Rakshitha Rao, Rashmi Rao, Shraddha, and Praveen J, "Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit," International Journal Of Advance Research And Innovative Ideas In Education, vol. 5, no. 2, pp. 2214-2220, Mar-App 2019. [Online]. Available: https://ijariie.com/AdminUploadPdf/Design_and_implementation_of_enhanced_sleepy_stack_with_LECTOR_technique_for_low_power_consumption_in_CMOS_VLSI_circuit_ijariie10018.pdf [Accessed : 14 July 2023].
Turabian Rahul Itnal, Rakshitha Rao, Rashmi Rao, Shraddha, and Praveen J. "Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 5 number 2 (14 July 2023).
Vancouver Rahul Itnal, Rakshitha Rao, Rashmi Rao, Shraddha, and Praveen J. Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuit. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2019 [Cited : 14 July 2023]; 5(2) : 2214-2220. Available from: https://ijariie.com/AdminUploadPdf/Design_and_implementation_of_enhanced_sleepy_stack_with_LECTOR_technique_for_low_power_consumption_in_CMOS_VLSI_circuit_ijariie10018.pdf
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