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Title: :  FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS
PaperId: :  13866
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 7 Issue 2 2021
DUI:    16.0415/IJARIIE-13866
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
Shankar RPrince Shri Venkateshwara Padmavathy Engineering College
Sundhararajan GPrince Shri Venkateshwara Padmavathy Engineering College
Vignesh SPrince Shri Venkateshwara Padmavathy Engineering College
Aravind ARPrince Shri Venkateshwara Padmavathy Engineering College

Abstract

Electronics and Communication Engineering
Karatsuba Multiplier, Vedic multiplier, Urdhva Triyakbhyam sutra, Area efficient architecture, Array multiplier
An area efficient multiplier design is conferred. This design is based on Karatsuba algorithm founded by Anatoly Karatsuba and ancient algorithm of Vedas, proposed within the Vedic mathematics. Multiplication is a very important mathematical operation to be performed with high speed and less power consumption in high-speed systems like Digital Signal Processing. The Karatsuba algorithm speed up the multiplication of large numbers by splitting the operands into two parts of equal length. In the Vedic multipliers the partial product generation and the also the sums are generated in few steps which reduces the carry propagation from LSB to MSB. In this proposed design the area and the delay is reduced. Finally, the results of Karatsuba Vedic multiplier is compared with Vedic multiplier.

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IJARIIE Shankar R, Sundhararajan G, Vignesh S, and Aravind AR. "FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS" International Journal Of Advance Research And Innovative Ideas In Education Volume 7 Issue 2 2021 Page 465-469
MLA Shankar R, Sundhararajan G, Vignesh S, and Aravind AR. "FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS." International Journal Of Advance Research And Innovative Ideas In Education 7.2(2021) : 465-469.
APA Shankar R, Sundhararajan G, Vignesh S, & Aravind AR. (2021). FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS. International Journal Of Advance Research And Innovative Ideas In Education, 7(2), 465-469.
Chicago Shankar R, Sundhararajan G, Vignesh S, and Aravind AR. "FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS." International Journal Of Advance Research And Innovative Ideas In Education 7, no. 2 (2021) : 465-469.
Oxford Shankar R, Sundhararajan G, Vignesh S, and Aravind AR. 'FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS', International Journal Of Advance Research And Innovative Ideas In Education, vol. 7, no. 2, 2021, p. 465-469. Available from IJARIIE, https://ijariie.com/AdminUploadPdf/FPGA_IMPLEMENTATION_OF_KARATSUBA_VEDIC_MULTIPLIERS_ijariie13866.pdf (Accessed : 30 March 2021).
Harvard Shankar R, Sundhararajan G, Vignesh S, and Aravind AR. (2021) 'FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS', International Journal Of Advance Research And Innovative Ideas In Education, 7(2), pp. 465-469IJARIIE [Online]. Available at: https://ijariie.com/AdminUploadPdf/FPGA_IMPLEMENTATION_OF_KARATSUBA_VEDIC_MULTIPLIERS_ijariie13866.pdf (Accessed : 30 March 2021)
IEEE Shankar R, Sundhararajan G, Vignesh S, and Aravind AR, "FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS," International Journal Of Advance Research And Innovative Ideas In Education, vol. 7, no. 2, pp. 465-469, Mar-App 2021. [Online]. Available: https://ijariie.com/AdminUploadPdf/FPGA_IMPLEMENTATION_OF_KARATSUBA_VEDIC_MULTIPLIERS_ijariie13866.pdf [Accessed : 30 March 2021].
Turabian Shankar R, Sundhararajan G, Vignesh S, and Aravind AR. "FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 7 number 2 (30 March 2021).
Vancouver Shankar R, Sundhararajan G, Vignesh S, and Aravind AR. FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2021 [Cited : 30 March 2021]; 7(2) : 465-469. Available from: https://ijariie.com/AdminUploadPdf/FPGA_IMPLEMENTATION_OF_KARATSUBA_VEDIC_MULTIPLIERS_ijariie13866.pdf
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