Call for Papers:Vol.11 Issue.3

Submission
Last date		 28-Jun-2025
Acceptance Status In One Day
Paper Publish In Two Days
Submit ManuScript

News & Updates

Submit Article

Dear Authors, Article publish in our journal for Volume-11,Issue-3. For article submission on below link: Submit Manuscript


Join As Board

Dear Reviewer, You can join our Reviewer team without given any charges in our journal. Submit Details on below link: Join As Board


Paper Publication Charges

IJARIIE APP
Download Android App

For Authors

Archives

IJARIIE Board

Downloads

Android App

Download IJARIIE APP

Authors

Title: :  ASIC Implementation Of PULP RISC-V Core
PaperId: :  17714
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 8 Issue 4 2022
DUI:    16.0415/IJARIIE-17714
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
Anirudh Rao MVidyavardhaka College Of Engineering
Manoj B MVidyavardhaka College Of Engineering
Monish V Vidyavardhaka College Of Engineering
N K SindhuVidyavardhaka College Of Engineering

Abstract

Electronics and Communication Engineering
RISC-V (Reduced Instruction Set), Harvard Architecture, ALU (Arithmetic and Logical Unit), Verilog, Cadence, Genus.
The microprocessor used in this project is built using the RISC-V CV32E40P architecture. According to the literature review, we discovered that the previously modified 32-bit CV32E40P manufactured at non-RISC-V has a frequency of 160 MHz, so the performance is insufficient for many out-of-the-box applications. Therefore, we chose to work on the processor's performance aspect in order to better support other applications of this type. By making various modifications to the physical design of the CV32E40P, we are attempting to increase the CPU clock speed in this project from 500MHz to 600MHz. In essence, by compromising on the power and surface area components of the CPU architecture, we are essentially sacrificing performance. In this project, we won't change the CV32E40P's RTL code because we'll improve processor performance by altering physical design factors like floor planning, proper placement, etc. We'll also put more of an emphasis on resolving issues that came up when we increased the CPU clock speed, such as noise, in addition to other problems.

Citations

Copy and paste a formatted citation or use one of the links to import into a bibliography manager and reference.

IJARIIE Anirudh Rao M, Manoj B M, Monish V , and N K Sindhu. "ASIC Implementation Of PULP RISC-V Core" International Journal Of Advance Research And Innovative Ideas In Education Volume 8 Issue 4 2022 Page 409-417
MLA Anirudh Rao M, Manoj B M, Monish V , and N K Sindhu. "ASIC Implementation Of PULP RISC-V Core." International Journal Of Advance Research And Innovative Ideas In Education 8.4(2022) : 409-417.
APA Anirudh Rao M, Manoj B M, Monish V , & N K Sindhu. (2022). ASIC Implementation Of PULP RISC-V Core. International Journal Of Advance Research And Innovative Ideas In Education, 8(4), 409-417.
Chicago Anirudh Rao M, Manoj B M, Monish V , and N K Sindhu. "ASIC Implementation Of PULP RISC-V Core." International Journal Of Advance Research And Innovative Ideas In Education 8, no. 4 (2022) : 409-417.
Oxford Anirudh Rao M, Manoj B M, Monish V , and N K Sindhu. 'ASIC Implementation Of PULP RISC-V Core', International Journal Of Advance Research And Innovative Ideas In Education, vol. 8, no. 4, 2022, p. 409-417. Available from IJARIIE, https://ijariie.com/AdminUploadPdf/ASIC_Implementation_Of_PULP_RISC_V_Core_ijariie17714.pdf (Accessed : 13 May 2025).
Harvard Anirudh Rao M, Manoj B M, Monish V , and N K Sindhu. (2022) 'ASIC Implementation Of PULP RISC-V Core', International Journal Of Advance Research And Innovative Ideas In Education, 8(4), pp. 409-417IJARIIE [Online]. Available at: https://ijariie.com/AdminUploadPdf/ASIC_Implementation_Of_PULP_RISC_V_Core_ijariie17714.pdf (Accessed : 13 May 2025)
IEEE Anirudh Rao M, Manoj B M, Monish V , and N K Sindhu, "ASIC Implementation Of PULP RISC-V Core," International Journal Of Advance Research And Innovative Ideas In Education, vol. 8, no. 4, pp. 409-417, Jul-Aug 2022. [Online]. Available: https://ijariie.com/AdminUploadPdf/ASIC_Implementation_Of_PULP_RISC_V_Core_ijariie17714.pdf [Accessed : 13 May 2025].
Turabian Anirudh Rao M, Manoj B M, Monish V , and N K Sindhu. "ASIC Implementation Of PULP RISC-V Core." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 8 number 4 (13 May 2025).
Vancouver Anirudh Rao M, Manoj B M, Monish V , and N K Sindhu. ASIC Implementation Of PULP RISC-V Core. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2022 [Cited : 13 May 2025]; 8(4) : 409-417. Available from: https://ijariie.com/AdminUploadPdf/ASIC_Implementation_Of_PULP_RISC_V_Core_ijariie17714.pdf
BibTex EndNote RefMan RefWorks

Number Of Downloads


Last download on 5/13/2025 5:39:31 AM

Save in Google Drive

Similar-Paper

TitleArea of ResearchAuther NameAction
Design Analysis and Implementation of Two Stage Operational AmplifierElectronics and Communication EngineeringRAJ KESARWANI Download
1X3 ROUTER RTL & UVM TESTBENCHElectronic and Telecommunication (VLSI BASED)MOHARIL ABOLI Download
ASIC Implementation Of PULP RISC-V CoreElectronics and Communication EngineeringAnirudh Rao M Download
FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERSElectronics and Communication EngineeringShankar R Download
Metastability Mitigation & Error Masking of Flip-FlopElectronics & CommunicationAPARNA Download
DESIGN OF CURRENT STARVED VCO USING POWER GATED INVERTER FOR PLLElectronics & Communication EngineeringMEENAKSHI TIWARI Download
LVDS Design for High speed ApplicationElectronicsAtharvan Boxey Download
virtual paintig through gesture detection and color segmentation technique using DE2 FPGA boardElctronics and telecommunication engineeringMs. Pooja Bcahhav Download
Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuitElectronics and communicationRahul Itnal Download
THRESHOLD LOGIC’S IMPORTANCE IN BUILDING EFFICIENT AND COMPACT DIGITAL CIRCUITS AND ITS SCOPE IN MODERN TECHNOLOGYELECTRONICS AND COMMUNICATION ENGINEERINGE.VENU BHAGIRATH Download
A Review on Dysarthria speech disorderelectonics and telecommunicationYogita S. Mahadik Download
FUNCTIONAL VERIFICATION OF USB 2.0 VIP USING SV- UVMELECTRONICS & TELECOMMUNICATIONKAMINI JHA Download
Implementation of IEC 61131-3 Standard Compatible instruction List Processor on FPGA PlatformVLSI designSagar Shedge Download
SPEED AND AREA EFFICIENT VLSI ARCHITECTURES FOR MPSK MODEMSELECTRONICS AND COMMUNICATION ENGINEERINGESTHER RANI C Download
180nm CMOS process based L-band CML to CMOS converterElectronics and CommunicationChirag Senjalliya Download
12