Call for Papers:Vol.10 Issue.6

Submission
Last date		 30-Dec-2024
Acceptance Status In One Day
Paper Publish In Two Days
Submit ManuScript

News & Updates

Submit Article

Dear Authors, Article publish in our journal for Volume-10,Issue-6. For article submission on below link: Submit Manuscript


Join As Board

Dear Reviewer, You can join our Reviewer team without given any charges in our journal. Submit Details on below link: Join As Board


Paper Publication Charges

IJARIIE APP
Download Android App

For Authors

Archives

IJARIIE Board

Downloads

Android App

Download IJARIIE APP

Authors

Title: :  1X3 ROUTER RTL & UVM TESTBENCH
PaperId: :  19849
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 9 Issue 2 2023
DUI:    16.0415/IJARIIE-19849
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
MOHARIL ABOLIShree L.R. Tiwari College Of Engineering
SINGH UTKARSH DINESHShree L.R. Tiwari College Of Engineering
RAORANE KRUNAL VIJAYShree L.R. Tiwari College Of Engineering
YADAV PRADEEP JANGBAHADURShree L.R. Tiwari College Of Engineering
YADAV DURGESH AMARJEETShree L.R. Tiwari College Of Engineering

Abstract

Electronic and Telecommunication (VLSI BASED)
Router, Top Model, FSM, FIFO, REG, SYNC, XILINX, ISIM, RTL, UVM
Abstract: This technical paper presents the design and implementation of a router using Verilog RTL. The router is capable of routing data packets from a source network to three different client networks. The design includes a register module to hold data packets momentarily and pass them on to three different First-In-First-Out (FIFO) memories, a Finite State Machine (FSM) module, and a Synchronizer module to manipulate internal signals for efficient task execution. The project was simulated using Xilinx ISE and ISIM, with code coverage analysis performed on Questa Sim. The RTL was verified through a Test Bench in a UVM-based environment. The router module was implemented using 130nm technology, with a packet width of 8 bits and a maximum packet length of 63 bytes. The top-level design and sub-modules were described, and the simulation and verification processes were detailed. The results showed that the FSM with a reduced number of states resulted in improved frequency response. The design can be extended to handle larger packet sizes and more client networks. This router implementation can be used in various networking applications, including the internet of things (IoT), industrial automation, and telecommunications.

Citations

Copy and paste a formatted citation or use one of the links to import into a bibliography manager and reference.

IJARIIE MOHARIL ABOLI, SINGH UTKARSH DINESH, RAORANE KRUNAL VIJAY, YADAV PRADEEP JANGBAHADUR, and YADAV DURGESH AMARJEET. "1X3 ROUTER RTL & UVM TESTBENCH" International Journal Of Advance Research And Innovative Ideas In Education Volume 9 Issue 2 2023 Page 2465-2471
MLA MOHARIL ABOLI, SINGH UTKARSH DINESH, RAORANE KRUNAL VIJAY, YADAV PRADEEP JANGBAHADUR, and YADAV DURGESH AMARJEET. "1X3 ROUTER RTL & UVM TESTBENCH." International Journal Of Advance Research And Innovative Ideas In Education 9.2(2023) : 2465-2471.
APA MOHARIL ABOLI, SINGH UTKARSH DINESH, RAORANE KRUNAL VIJAY, YADAV PRADEEP JANGBAHADUR, & YADAV DURGESH AMARJEET. (2023). 1X3 ROUTER RTL & UVM TESTBENCH. International Journal Of Advance Research And Innovative Ideas In Education, 9(2), 2465-2471.
Chicago MOHARIL ABOLI, SINGH UTKARSH DINESH, RAORANE KRUNAL VIJAY, YADAV PRADEEP JANGBAHADUR, and YADAV DURGESH AMARJEET. "1X3 ROUTER RTL & UVM TESTBENCH." International Journal Of Advance Research And Innovative Ideas In Education 9, no. 2 (2023) : 2465-2471.
Oxford MOHARIL ABOLI, SINGH UTKARSH DINESH, RAORANE KRUNAL VIJAY, YADAV PRADEEP JANGBAHADUR, and YADAV DURGESH AMARJEET. '1X3 ROUTER RTL & UVM TESTBENCH', International Journal Of Advance Research And Innovative Ideas In Education, vol. 9, no. 2, 2023, p. 2465-2471. Available from IJARIIE, https://ijariie.com/AdminUploadPdf/1X3_ROUTER_RTL___UVM_TESTBENCH_ijariie19849.pdf (Accessed : 14 October 2024).
Harvard MOHARIL ABOLI, SINGH UTKARSH DINESH, RAORANE KRUNAL VIJAY, YADAV PRADEEP JANGBAHADUR, and YADAV DURGESH AMARJEET. (2023) '1X3 ROUTER RTL & UVM TESTBENCH', International Journal Of Advance Research And Innovative Ideas In Education, 9(2), pp. 2465-2471IJARIIE [Online]. Available at: https://ijariie.com/AdminUploadPdf/1X3_ROUTER_RTL___UVM_TESTBENCH_ijariie19849.pdf (Accessed : 14 October 2024)
IEEE MOHARIL ABOLI, SINGH UTKARSH DINESH, RAORANE KRUNAL VIJAY, YADAV PRADEEP JANGBAHADUR, and YADAV DURGESH AMARJEET, "1X3 ROUTER RTL & UVM TESTBENCH," International Journal Of Advance Research And Innovative Ideas In Education, vol. 9, no. 2, pp. 2465-2471, Mar-App 2023. [Online]. Available: https://ijariie.com/AdminUploadPdf/1X3_ROUTER_RTL___UVM_TESTBENCH_ijariie19849.pdf [Accessed : 14 October 2024].
Turabian MOHARIL ABOLI, SINGH UTKARSH DINESH, RAORANE KRUNAL VIJAY, YADAV PRADEEP JANGBAHADUR, and YADAV DURGESH AMARJEET. "1X3 ROUTER RTL & UVM TESTBENCH." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 9 number 2 (14 October 2024).
Vancouver MOHARIL ABOLI, SINGH UTKARSH DINESH, RAORANE KRUNAL VIJAY, YADAV PRADEEP JANGBAHADUR, and YADAV DURGESH AMARJEET. 1X3 ROUTER RTL & UVM TESTBENCH. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2023 [Cited : 14 October 2024]; 9(2) : 2465-2471. Available from: https://ijariie.com/AdminUploadPdf/1X3_ROUTER_RTL___UVM_TESTBENCH_ijariie19849.pdf
BibTex EndNote RefMan RefWorks

Number Of Downloads


Last download on 10/14/2024 2:20:59 PM

Save in Google Drive

Similar-Paper

TitleArea of ResearchAuther NameAction
Design Analysis and Implementation of Two Stage Operational AmplifierElectronics and Communication EngineeringRAJ KESARWANI Download
1X3 ROUTER RTL & UVM TESTBENCHElectronic and Telecommunication (VLSI BASED)MOHARIL ABOLI Download
ASIC Implementation Of PULP RISC-V CoreElectronics and Communication EngineeringAnirudh Rao M Download
FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERSElectronics and Communication EngineeringShankar R Download
Metastability Mitigation & Error Masking of Flip-FlopElectronics & CommunicationAPARNA Download
DESIGN OF CURRENT STARVED VCO USING POWER GATED INVERTER FOR PLLElectronics & Communication EngineeringMEENAKSHI TIWARI Download
LVDS Design for High speed ApplicationElectronicsAtharvan Boxey Download
virtual paintig through gesture detection and color segmentation technique using DE2 FPGA boardElctronics and telecommunication engineeringMs. Pooja Bcahhav Download
Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuitElectronics and communicationRahul Itnal Download
THRESHOLD LOGIC’S IMPORTANCE IN BUILDING EFFICIENT AND COMPACT DIGITAL CIRCUITS AND ITS SCOPE IN MODERN TECHNOLOGYELECTRONICS AND COMMUNICATION ENGINEERINGE.VENU BHAGIRATH Download
A Review on Dysarthria speech disorderelectonics and telecommunicationYogita S. Mahadik Download
FUNCTIONAL VERIFICATION OF USB 2.0 VIP USING SV- UVMELECTRONICS & TELECOMMUNICATIONKAMINI JHA Download
Implementation of IEC 61131-3 Standard Compatible instruction List Processor on FPGA PlatformVLSI designSagar Shedge Download
SPEED AND AREA EFFICIENT VLSI ARCHITECTURES FOR MPSK MODEMSELECTRONICS AND COMMUNICATION ENGINEERINGESTHER RANI C Download
180nm CMOS process based L-band CML to CMOS converterElectronics and CommunicationChirag Senjalliya Download
12