Call for Papers:Vol.10 Issue.6

Submission
Last date		 30-Dec-2024
Acceptance Status In One Day
Paper Publish In Two Days
Submit ManuScript

News & Updates

Submit Article

Dear Authors, Article publish in our journal for Volume-10,Issue-6. For article submission on below link: Submit Manuscript


Join As Board

Dear Reviewer, You can join our Reviewer team without given any charges in our journal. Submit Details on below link: Join As Board


Paper Publication Charges

IJARIIE APP
Download Android App

For Authors

Archives

IJARIIE Board

Downloads

Android App

Download IJARIIE APP

Authors

Title: :  Design Analysis and Implementation of Two Stage Operational Amplifier
PaperId: :  24018
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 10 Issue 3 2024
DUI:    16.0415/IJARIIE-24018
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
RAJ KESARWANIABES ENGINEERING COLLEGE, GHAZIABAD
RAHUL PANDEYABES ENGINEERING COLLEGE, GHAZIABAD
SAHIL AGARWALABES ENGINEERING COLLEGE, GHAZIABAD
SHAILENDRA BISARIYAABES ENGINEERING COLLEGE, GHAZIABAD
MUDIT SAXENAABES ENGINEERING COLLEGE, GHAZIABAD

Abstract

Electronics and Communication Engineering
gain, Op amp, Cadence, 90nm, Op amp, CMOS
The operational amplifier is regarded as the most crucial electronic component. This paper outlines the process for designing a two-stage CMOS operational amplifier (Op amp) and examine how different factors affect the Op amp design's properties. The primary focus of this study is the design of an optimum Op amp gain. Op amp specs are considered, including gain, phase margin, slew rate, power dissipation, and others, while keeping this as the primary consideration. The design and implementation of a two-stage CMOS operational amplifier, operating at ±1V supply voltage, are shown in this study. The simulation process is performed using an EDA program called Cadence Virtuoso, which uses 90nm technology. With a phase margin of 560 and a power dissipation of 38.02μW, the resultant gain is 84db.

Citations

Copy and paste a formatted citation or use one of the links to import into a bibliography manager and reference.

IJARIIE RAJ KESARWANI, RAHUL PANDEY, SAHIL AGARWAL, SHAILENDRA BISARIYA, and MUDIT SAXENA. "Design Analysis and Implementation of Two Stage Operational Amplifier" International Journal Of Advance Research And Innovative Ideas In Education Volume 10 Issue 3 2024 Page 4210-4217
MLA RAJ KESARWANI, RAHUL PANDEY, SAHIL AGARWAL, SHAILENDRA BISARIYA, and MUDIT SAXENA. "Design Analysis and Implementation of Two Stage Operational Amplifier." International Journal Of Advance Research And Innovative Ideas In Education 10.3(2024) : 4210-4217.
APA RAJ KESARWANI, RAHUL PANDEY, SAHIL AGARWAL, SHAILENDRA BISARIYA, & MUDIT SAXENA. (2024). Design Analysis and Implementation of Two Stage Operational Amplifier. International Journal Of Advance Research And Innovative Ideas In Education, 10(3), 4210-4217.
Chicago RAJ KESARWANI, RAHUL PANDEY, SAHIL AGARWAL, SHAILENDRA BISARIYA, and MUDIT SAXENA. "Design Analysis and Implementation of Two Stage Operational Amplifier." International Journal Of Advance Research And Innovative Ideas In Education 10, no. 3 (2024) : 4210-4217.
Oxford RAJ KESARWANI, RAHUL PANDEY, SAHIL AGARWAL, SHAILENDRA BISARIYA, and MUDIT SAXENA. 'Design Analysis and Implementation of Two Stage Operational Amplifier', International Journal Of Advance Research And Innovative Ideas In Education, vol. 10, no. 3, 2024, p. 4210-4217. Available from IJARIIE, https://ijariie.com/AdminUploadPdf/Design_Analysis_and_Implementation_of_Two_Stage__Operational_Amplifier_ijariie24012.pdf (Accessed : 13 August 2024).
Harvard RAJ KESARWANI, RAHUL PANDEY, SAHIL AGARWAL, SHAILENDRA BISARIYA, and MUDIT SAXENA. (2024) 'Design Analysis and Implementation of Two Stage Operational Amplifier', International Journal Of Advance Research And Innovative Ideas In Education, 10(3), pp. 4210-4217IJARIIE [Online]. Available at: https://ijariie.com/AdminUploadPdf/Design_Analysis_and_Implementation_of_Two_Stage__Operational_Amplifier_ijariie24012.pdf (Accessed : 13 August 2024)
IEEE RAJ KESARWANI, RAHUL PANDEY, SAHIL AGARWAL, SHAILENDRA BISARIYA, and MUDIT SAXENA, "Design Analysis and Implementation of Two Stage Operational Amplifier," International Journal Of Advance Research And Innovative Ideas In Education, vol. 10, no. 3, pp. 4210-4217, May-Jun 2024. [Online]. Available: https://ijariie.com/AdminUploadPdf/Design_Analysis_and_Implementation_of_Two_Stage__Operational_Amplifier_ijariie24012.pdf [Accessed : 13 August 2024].
Turabian RAJ KESARWANI, RAHUL PANDEY, SAHIL AGARWAL, SHAILENDRA BISARIYA, and MUDIT SAXENA. "Design Analysis and Implementation of Two Stage Operational Amplifier." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 10 number 3 (13 August 2024).
Vancouver RAJ KESARWANI, RAHUL PANDEY, SAHIL AGARWAL, SHAILENDRA BISARIYA, and MUDIT SAXENA. Design Analysis and Implementation of Two Stage Operational Amplifier. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2024 [Cited : 13 August 2024]; 10(3) : 4210-4217. Available from: https://ijariie.com/AdminUploadPdf/Design_Analysis_and_Implementation_of_Two_Stage__Operational_Amplifier_ijariie24012.pdf
BibTex EndNote RefMan RefWorks

Number Of Downloads


Last download on 8/13/2024 5:03:12 PM

Save in Google Drive

Similar-Paper

TitleArea of ResearchAuther NameAction
Design Analysis and Implementation of Two Stage Operational AmplifierElectronics and Communication EngineeringRAJ KESARWANI Download
1X3 ROUTER RTL & UVM TESTBENCHElectronic and Telecommunication (VLSI BASED)MOHARIL ABOLI Download
ASIC Implementation Of PULP RISC-V CoreElectronics and Communication EngineeringAnirudh Rao M Download
FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERSElectronics and Communication EngineeringShankar R Download
Metastability Mitigation & Error Masking of Flip-FlopElectronics & CommunicationAPARNA Download
DESIGN OF CURRENT STARVED VCO USING POWER GATED INVERTER FOR PLLElectronics & Communication EngineeringMEENAKSHI TIWARI Download
LVDS Design for High speed ApplicationElectronicsAtharvan Boxey Download
virtual paintig through gesture detection and color segmentation technique using DE2 FPGA boardElctronics and telecommunication engineeringMs. Pooja Bcahhav Download
Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuitElectronics and communicationRahul Itnal Download
THRESHOLD LOGIC’S IMPORTANCE IN BUILDING EFFICIENT AND COMPACT DIGITAL CIRCUITS AND ITS SCOPE IN MODERN TECHNOLOGYELECTRONICS AND COMMUNICATION ENGINEERINGE.VENU BHAGIRATH Download
A Review on Dysarthria speech disorderelectonics and telecommunicationYogita S. Mahadik Download
FUNCTIONAL VERIFICATION OF USB 2.0 VIP USING SV- UVMELECTRONICS & TELECOMMUNICATIONKAMINI JHA Download
Implementation of IEC 61131-3 Standard Compatible instruction List Processor on FPGA PlatformVLSI designSagar Shedge Download
SPEED AND AREA EFFICIENT VLSI ARCHITECTURES FOR MPSK MODEMSELECTRONICS AND COMMUNICATION ENGINEERINGESTHER RANI C Download
180nm CMOS process based L-band CML to CMOS converterElectronics and CommunicationChirag Senjalliya Download
12