Call for Papers:Vol.12 Issue.2

Submission
Last date		 28-Apr-2026
Acceptance Status In One Day
Paper Publish In Two Days
Submit ManuScript

News & Updates

Submit Article

Dear Authors, Article publish in our journal for Volume-12,Issue-2. For article submission on below link: Submit Manuscript


Join As Board

Dear Reviewer, You can join our Reviewer team without given any charges in our journal. Submit Details on below link: Join As Board


Paper Publication Charges

IJARIIE APP
Download Android App

For Authors

Archives

IJARIIE Board

Downloads

Android App

Download IJARIIE APP

Authors

Title: :  IMPROVING TEST COVERAGE OF SCL USING TEST POINT INSERTION
PaperId: :  5698
Published in:   International Journal Of Advance Research And Innovative Ideas In Education
Publisher:   IJARIIE
e-ISSN:   2395-4396
Volume/Issue:    Volume 3 Issue 3 2017
DUI:    16.0415/IJARIIE-5698
Licence: :   IJARIIE is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author NameAuthor Institute
SRUTHI M SMETS SCHOOL OF ENGINEERING
FEMIN TREASAMETS SCHOOL OF ENGINEERING

Abstract

VLSI DESIGN
Design for testability (DFT), Sleep convention logic (SCL), Null convention logic (NCL), Multi threshold complementary metal oxide semiconductor (MTCMOS), Test point insertion (TPI), Scan cells.
IC testing is one of the most important steps in today's complex system-on-chip design. After manufacturing, if an IC failed in performing when applied in real condition it will increase the cost for manufacturing and also increases the time of design. So this testing should be done before the manufacturing. Sleep Convention Logic is a promising Asynchronous Logic Style. And its design is a combination of Multi Threshold CMOS design and Null Convention Logic. Its architecture is different from the NCL therefore a new design for testability should be proposed. Scan cell based DFT is proposed here and to improve its test coverage an additional Test Point Insertion technique is included.

Citations

Copy and paste a formatted citation or use one of the links to import into a bibliography manager and reference.

IJARIIE SRUTHI M S, and FEMIN TREASA. "IMPROVING TEST COVERAGE OF SCL USING TEST POINT INSERTION" International Journal Of Advance Research And Innovative Ideas In Education Volume 3 Issue 3 2017 Page 3410-3418
MLA SRUTHI M S, and FEMIN TREASA. "IMPROVING TEST COVERAGE OF SCL USING TEST POINT INSERTION." International Journal Of Advance Research And Innovative Ideas In Education 3.3(2017) : 3410-3418.
APA SRUTHI M S, & FEMIN TREASA. (2017). IMPROVING TEST COVERAGE OF SCL USING TEST POINT INSERTION. International Journal Of Advance Research And Innovative Ideas In Education, 3(3), 3410-3418.
Chicago SRUTHI M S, and FEMIN TREASA. "IMPROVING TEST COVERAGE OF SCL USING TEST POINT INSERTION." International Journal Of Advance Research And Innovative Ideas In Education 3, no. 3 (2017) : 3410-3418.
Oxford SRUTHI M S, and FEMIN TREASA. 'IMPROVING TEST COVERAGE OF SCL USING TEST POINT INSERTION', International Journal Of Advance Research And Innovative Ideas In Education, vol. 3, no. 3, 2017, p. 3410-3418. Available from IJARIIE, https://ijariie.com/AdminUploadPdf/IMPROVING_TEST_COVERAGE_OF_SCL_USING_TEST_POINT_INSERTION_ijariie5698.pdf (Accessed : 04 July 2017).
Harvard SRUTHI M S, and FEMIN TREASA. (2017) 'IMPROVING TEST COVERAGE OF SCL USING TEST POINT INSERTION', International Journal Of Advance Research And Innovative Ideas In Education, 3(3), pp. 3410-3418IJARIIE [Online]. Available at: https://ijariie.com/AdminUploadPdf/IMPROVING_TEST_COVERAGE_OF_SCL_USING_TEST_POINT_INSERTION_ijariie5698.pdf (Accessed : 04 July 2017)
IEEE SRUTHI M S, and FEMIN TREASA, "IMPROVING TEST COVERAGE OF SCL USING TEST POINT INSERTION," International Journal Of Advance Research And Innovative Ideas In Education, vol. 3, no. 3, pp. 3410-3418, May-Jun 2017. [Online]. Available: https://ijariie.com/AdminUploadPdf/IMPROVING_TEST_COVERAGE_OF_SCL_USING_TEST_POINT_INSERTION_ijariie5698.pdf [Accessed : 04 July 2017].
Turabian SRUTHI M S, and FEMIN TREASA. "IMPROVING TEST COVERAGE OF SCL USING TEST POINT INSERTION." International Journal Of Advance Research And Innovative Ideas In Education [Online]. volume 3 number 3 (04 July 2017).
Vancouver SRUTHI M S, and FEMIN TREASA. IMPROVING TEST COVERAGE OF SCL USING TEST POINT INSERTION. International Journal Of Advance Research And Innovative Ideas In Education [Internet]. 2017 [Cited : 04 July 2017]; 3(3) : 3410-3418. Available from: https://ijariie.com/AdminUploadPdf/IMPROVING_TEST_COVERAGE_OF_SCL_USING_TEST_POINT_INSERTION_ijariie5698.pdf
BibTex EndNote RefMan RefWorks

Number Of Downloads


Last download on 7/4/2017 4:28:06 AM

Save in Google Drive

Similar-Paper

TitleArea of ResearchAuther NameAction
Design Analysis and Implementation of Two Stage Operational AmplifierElectronics and Communication EngineeringRAJ KESARWANI Download
1X3 ROUTER RTL & UVM TESTBENCHElectronic and Telecommunication (VLSI BASED)MOHARIL ABOLI Download
ASIC Implementation Of PULP RISC-V CoreElectronics and Communication EngineeringAnirudh Rao M Download
FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERSElectronics and Communication EngineeringShankar R Download
Metastability Mitigation & Error Masking of Flip-FlopElectronics & CommunicationAPARNA Download
DESIGN OF CURRENT STARVED VCO USING POWER GATED INVERTER FOR PLLElectronics & Communication EngineeringMEENAKSHI TIWARI Download
LVDS Design for High speed ApplicationElectronicsAtharvan Boxey Download
virtual paintig through gesture detection and color segmentation technique using DE2 FPGA boardElctronics and telecommunication engineeringMs. Pooja Bcahhav Download
Design and implementation of enhanced sleepy stack with LECTOR technique for low power consumption in CMOS VLSI circuitElectronics and communicationRahul Itnal Download
THRESHOLD LOGIC’S IMPORTANCE IN BUILDING EFFICIENT AND COMPACT DIGITAL CIRCUITS AND ITS SCOPE IN MODERN TECHNOLOGYELECTRONICS AND COMMUNICATION ENGINEERINGE.VENU BHAGIRATH Download
A Review on Dysarthria speech disorderelectonics and telecommunicationYogita S. Mahadik Download
FUNCTIONAL VERIFICATION OF USB 2.0 VIP USING SV- UVMELECTRONICS & TELECOMMUNICATIONKAMINI JHA Download
Implementation of IEC 61131-3 Standard Compatible instruction List Processor on FPGA PlatformVLSI designSagar Shedge Download
SPEED AND AREA EFFICIENT VLSI ARCHITECTURES FOR MPSK MODEMSELECTRONICS AND COMMUNICATION ENGINEERINGESTHER RANI C Download
180nm CMOS process based L-band CML to CMOS converterElectronics and CommunicationChirag Senjalliya Download
12